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SN74LVCH16901

更新时间： 2024-11-23 23:06:23
品牌 Logo 应用领域
德州仪器 - TI 总线收发器
页数 文件大小 规格书
11页 157K
描述
18-BIT UNIVERSAL BUS TRANSCEIVER WITH PARITY GENERATORS/CHECKERS

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SN74LVCH16901 数据手册

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SN74LVCH16901  
18-BIT UNIVERSAL BUS TRANSCEIVER  
WITH PARITY GENERATORS/CHECKERS  
SCES145A – OCTOBER 1998 – REVISED MAY 1999  
DGG PACKAGE  
(TOP VIEW)  
Member of the Texas Instruments  
Widebus+ Family  
EPIC (Enhanced-Performance Implanted  
CMOS) Submicron Process  
1CLKENAB  
LEAB  
CLKAB  
1ERRA  
1APAR  
GND  
1CLKENBA  
LEBA  
CLKBA  
1ERRB  
1BPAR  
GND  
1B1  
1B2  
1B3  
1
64  
63  
62  
61  
60  
59  
58  
57  
56  
55  
54  
53  
52  
51  
50  
49  
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
2
UBT (Universal Bus Transceiver)  
Combines D-Type Latches and D-Type  
Flip-Flops for Operation in Transparent,  
Latched, or Clocked Mode  
3
4
5
6
Typical V  
< 0.8 V at V  
(Output Ground Bounce)  
1A1  
1A2  
1A3  
7
OLP  
= 3.3 V, T = 25°C  
8
CC  
A
9
Typical V  
> 2 V at V  
(Output V  
Undershoot)  
OHV  
CC  
OH  
V
V
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
32  
= 3.3 V, T = 25°C  
CC  
CC  
A
1A4  
1A5  
1A6  
GND  
1A7  
1A8  
2A1  
2A2  
GND  
2A3  
2A4  
2A5  
1B4  
1B5  
1B6  
GND  
1B7  
1B8  
2B1  
2B2  
GND  
2B3  
2B4  
2B5  
Simultaneously Generates and Checks  
Parity  
Option to Select Generate Parity and Check  
or Feed-Through Data/Parity in A-to-B or  
B-to-A Directions  
Supports Mixed-Mode Signal Operation on  
All Ports (5-V Input/Output Voltage With  
3.3-V V  
)
CC  
I
Supports Partial-Power-Down-Mode  
off  
Operation  
ESD Protection Exceeds 2000 V Per  
MIL-STD-883, Method 3015; Exceeds 200 V  
Using Machine Model (C = 200 pF, R = 0)  
V
V
CC  
CC  
2A6  
2A7  
2A8  
2B6  
2B7  
2B8  
GND  
2BPAR  
2ERRB  
OEBA  
ODD/EVEN  
2CLKENBA  
Latch-Up Performance Exceeds 100 mA Per  
JESD 78, Class I  
GND  
Bus Hold on Data Inputs Eliminates the  
Need for External Pullup/Pulldown  
Resistors  
2APAR  
2ERRA  
OEAB  
SEL  
Packaged in Thin Shrink Small-Outline  
Package  
2CLKENAB  
description  
This 18-bit (dual-octal) noninverting registered transceiver is designed for 1.65-V to 3.6-V V  
operation.  
CC  
The SN74LVCH16901 is a dual 9-bit to dual 9-bit parity transceiver with registers. The device can operate as  
a feed-through transceiver, or it can generate/check parity from the two 8-bit data buses in either direction.  
The SN74LVCH16901 features independent clock (CLKAB or CLKBA), latch-enable (LEAB or LEBA), and dual  
9-bit clock-enable (CLKENAB or CLKENBA) inputs. It also provides parity-enable (SEL) and parity-select  
(ODD/EVEN) inputs and separate error-signal (ERRA or ERRB) outputs for checking parity. The direction of  
data flow is controlled by output-enable (OEAB and OEBA) inputs. When SEL is low, the parity functions are  
enabled. When SEL is high, the parity functions are disabled, and the device acts as an 18-bit registered  
transceiver.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Widebus+, EPIC, and UBT are trademarks of Texas Instruments Incorporated.  
Copyright 1999, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...11

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