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SN74LVCH16374AGRDR PDF预览

SN74LVCH16374AGRDR

更新时间: 2024-11-24 04:00:55
品牌 Logo 应用领域
德州仪器 - TI 总线驱动器总线收发器触发器逻辑集成电路输出元件
页数 文件大小 规格书
15页 333K
描述
16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS

SN74LVCH16374AGRDR 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:BGA
包装说明:PLASTIC, FBGA-54针数:54
Reach Compliance Code:not_compliantHTS代码:8542.39.00.01
风险等级:5.75Is Samacsys:N
系列:LVC/LCX/ZJESD-30 代码:R-PBGA-B54
长度:8 mm负载电容(CL):50 pF
逻辑集成电路类型:BUS DRIVER最大频率@ Nom-Sup:150000000 Hz
最大I(ol):0.024 A位数:8
功能数量:2端口数量:2
端子数量:54最高工作温度:85 °C
最低工作温度:-40 °C输出特性:3-STATE
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:TFBGA封装等效代码:BGA54,6X9,32
封装形状:RECTANGULAR封装形式:GRID ARRAY, THIN PROFILE, FINE PITCH
包装方法:TAPE AND REEL峰值回流温度(摄氏度):NOT SPECIFIED
电源:3.3 VProp。Delay @ Nom-Sup:4.5 ns
传播延迟(tpd):4.9 ns认证状态:Not Qualified
座面最大高度:1.2 mm子类别:FF/Latches
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):1.65 V
标称供电电压 (Vsup):1.8 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子形式:BALL端子节距:0.8 mm
端子位置:BOTTOM处于峰值回流温度下的最长时间:NOT SPECIFIED
触发器类型:POSITIVE EDGE宽度:5.5 mm
Base Number Matches:1

SN74LVCH16374AGRDR 数据手册

 浏览型号SN74LVCH16374AGRDR的Datasheet PDF文件第2页浏览型号SN74LVCH16374AGRDR的Datasheet PDF文件第3页浏览型号SN74LVCH16374AGRDR的Datasheet PDF文件第4页浏览型号SN74LVCH16374AGRDR的Datasheet PDF文件第5页浏览型号SN74LVCH16374AGRDR的Datasheet PDF文件第6页浏览型号SN74LVCH16374AGRDR的Datasheet PDF文件第7页 
SN74LVCH16374A  
16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP  
WITH 3-STATE OUTPUTS  
www.ti.com  
SCAS757ADECEMBER 2003REVISED OCTOBER 2005  
FEATURES  
DGG, DGV, OR DL PACKAGE  
(TOP VIEW)  
Member of the Texas Instruments Widebus™  
Family  
1
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
1CLK  
1D1  
1D2  
GND  
1D3  
1D4  
1OE  
1Q1  
1Q2  
GND  
1Q3  
1Q4  
Operates From 1.65 V to 3.6 V  
Inputs Accept Voltages to 5.5 V  
Max tpd of 4.5 ns at 3.3 V  
2
3
4
Typical VOLP (Output Ground Bounce) <0.8 V  
at VCC = 3.3 V, TA = 25°C  
5
6
Typical VOHV (Output VOH Undershoot) >2 V at  
VCC = 3.3 V, TA = 25°C  
7
V
CC  
V
CC  
8
1D5  
1D6  
GND  
1D7  
1D8  
2D1  
2D2  
GND  
2D3  
2D4  
1Q5  
1Q6  
GND  
1Q7  
1Q8  
2Q1  
2Q2  
GND  
2Q3  
2Q4  
9
Ioff Supports Partial-Power-Down Mode  
Operation  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
Supports Mixed-Mode Signal Operation on All  
Ports (5-V Input and Output Voltages With  
3.3-V VCC  
)
Bus Hold on Data Inputs Eliminates the Need  
for External Pullup/Pulldown Resistors  
Latch-Up Performance Exceeds 250 mA Per  
JESD 17  
V
CC  
V
CC  
ESD Protection Exceeds JESD 22  
2D5  
2D6  
GND  
2D7  
2D8  
2CLK  
2Q5  
2Q6  
GND  
2Q7  
2Q8  
2OE  
– 2000-V Human-Body Model (A114-A)  
– 1000-V Charged-Device Model (C101)  
DESCRIPTION/ORDERING INFORMATION  
This 16-bit edge-triggered D-type flip-flop is designed  
for 1.65-V to 3.6-V VCC operation.  
ORDERING INFORMATION  
TA  
PACKAGE(1)  
ORDERABLE PART NUMBER  
SN74LVCH16374AGRDR  
SN74LVCH16374AZRDR  
SN74LVCH16374ADL  
TOP-SIDE MARKING  
FBGA – GRD  
Tape and reel  
Tube  
LDH374A  
FBGA – ZRD (Pb-free)  
74LVCH16374ADLG4  
SSOP – DL  
LVCH16374A  
SN74LVCH16374ADL  
Tape and reel  
Tape and reel  
Tape and reel  
Tape and reel  
74LVCH16374ADLRG4  
SN74LVCH16374ADGGR  
74LVCH16374ADGGRG4  
SN74LVCH16374ADGVR  
74LVCH16374ADGVRE4  
SN74LVCH16374AGQLR  
SN74LVCH16374AZQLR  
–40°C to 85°C  
TSSOP – DGG  
TVSOP – DGV  
LVCH16374A  
LDH374A  
VFBGA – GQL  
LDH374A  
VFBGA – ZQL (Pb-free)  
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at  
www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Widebus is a trademark of Texas Instruments.  
PRODUCTION DATA information is current as of publication date.  
Copyright © 2003–2005, Texas Instruments Incorporated  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  

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