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SN74LVCH16374ADL

更新时间： 2024-11-26 23:06:23
品牌 Logo 应用领域
德州仪器 - TI 总线驱动器总线收发器触发器逻辑集成电路光电二极管输出元件
页数 文件大小 规格书
10页 153K
描述
16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS

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中文翻译

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SN74LVCH16374ADL 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：SSOP
包装说明：SSOP-48针数：48
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01Factory Lead Time：1 week
风险等级：1.69Is Samacsys：N
控制类型：INDEPENDENT CONTROL计数方向：UNIDIRECTIONAL
系列：LVC/LCX/ZJESD-30 代码：R-PDSO-G48
JESD-609代码：e4长度：15.875 mm
负载电容（CL）：50 pF逻辑集成电路类型：BUS DRIVER
最大频率@ Nom-Sup：150000000 Hz最大I（ol）：0.024 A
湿度敏感等级：1位数：8
功能数量：2端口数量：2
端子数量：48最高工作温度：125 °C
最低工作温度：-40 °C输出特性：3-STATE
输出极性：TRUE封装主体材料：PLASTIC/EPOXY
封装代码：SSOP封装等效代码：SSOP48,.4
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, SHRINK PITCH
包装方法：TUBE峰值回流温度（摄氏度）：260
电源：3.3 V最大电源电流（ICC）：0.02 mA
Prop。Delay @ Nom-Sup：4.5 ns传播延迟（tpd）：4.9 ns
认证状态：Not Qualified座面最大高度：2.79 mm
子类别：FF/Latches最大供电电压 (Vsup)：3.6 V
最小供电电压 (Vsup)：1.65 V标称供电电压 (Vsup)：1.8 V
表面贴装：YES技术：CMOS
温度等级：AUTOMOTIVE端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：GULL WING端子节距：0.635 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
翻译：N/A触发器类型：POSITIVE EDGE
宽度：7.49 mmBase Number Matches：1

SN74LVCH16374ADL 数据手册

 浏览型号SN74LVCH16374ADL的Datasheet PDF文件第2页浏览型号SN74LVCH16374ADL的Datasheet PDF文件第3页浏览型号SN74LVCH16374ADL的Datasheet PDF文件第4页浏览型号SN74LVCH16374ADL的Datasheet PDF文件第5页浏览型号SN74LVCH16374ADL的Datasheet PDF文件第6页浏览型号SN74LVCH16374ADL的Datasheet PDF文件第7页 
SN74LVCH16374A  
16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP  
WITH 3-STATE OUTPUTS  
SCAS565F – MARCH 1996 – REVISED JUNE 1998  
DGG OR DL PACKAGE  
(TOP VIEW)  
Member of the Texas Instruments  
Widebus Family  
EPIC (Enhanced-Performance Implanted  
CMOS) Submicron Process  
1
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
1OE  
1Q1  
1Q2  
GND  
1Q3  
1Q4  
1CLK  
1D1  
1D2  
GND  
1D3  
1D4  
2
Typical V  
< 0.8 V at V  
(Output Ground Bounce)  
OLP  
3
= 3.3 V, T = 25°C  
CC  
A
4
Typical V  
> 2 V at V  
(Output V  
Undershoot)  
OHV  
CC  
OH  
5
= 3.3 V, T = 25°C  
A
6
Power Off Disables Outputs, Permitting  
Live Insertion  
7
V
V
CC  
CC  
8
1Q5  
1Q6  
GND  
1Q7  
1Q8  
2Q1  
2Q2  
GND  
2Q3  
2Q4  
1D5  
1D6  
GND  
1D7  
1D8  
2D1  
2D2  
GND  
2D3  
2D4  
9
Supports Mixed-Mode Signal Operation on  
All Ports (5-V Input and Output Voltages  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
With 3.3-V V  
)
CC  
Latch-Up Performance Exceeds 250 mA Per  
JESD 17  
Bus Hold on Data Inputs Eliminates the  
Need for External Pullup/Pulldown  
Resistors  
Package Options Include Plastic 300-mil  
Shrink Small-Outline (DL) and Thin Shrink  
Small-Outline (DGG) Packages  
V
V
CC  
CC  
2Q5  
2Q6  
GND  
2Q7  
2Q8  
2OE  
2D5  
2D6  
GND  
2D7  
2D8  
2CLK  
description  
This 16-bit edge-triggered D-type flip-flop is  
designed for 1.65-V to 3.6-V V operation.  
CC  
The SN74LVCH16374A is particularly suitable for  
implementing buffer registers, I/O ports,  
bidirectional bus drivers, and working registers. It  
can be used as two 8-bit flip-flops or one 16-bit  
flip-flop. On the positive transition of the clock  
(CLK) input, the Q outputs of the flip-flop take on  
the logic levels set up at the data (D) inputs.  
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high  
or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive  
thebuslinessignificantly. Thehigh-impedancestateandincreaseddriveprovidethecapabilitytodrivebuslines  
without interface or pullup components.  
OE does not affect internal operations of the flip-flop. Old data can be retained or new data can be entered while  
the outputs are in the high-impedance state.  
To ensure the high-impedance state during power up or power down, OE should be tied to V through a pullup  
CC  
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.  
Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators  
in a mixed 3.3-V/5-V system environment.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
EPIC and Widebus are trademarks of Texas Instruments Incorporated.  
Copyright 1998, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...10

中文翻译

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SN74LVCH16374ADL 替代型号

型号 品牌 替代类型 描述 数据表
SN74LVCH16374ADLR TI

类似代替

 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS
74LVCH16374ADLRG4 TI

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 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS
74LVCH16374ADLG4 TI

类似代替

 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS

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