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SN74LVCH16373A

更新时间： 2024-09-14 23:06:23
品牌 Logo 应用领域
德州仪器 - TI 锁存器输出元件
页数 文件大小 规格书
13页 303K
描述
16-BIT TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS

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SN74LVCH16373A 数据手册

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SCAS568L − MARCH 1996 − REVISED SEPTEMBER 2003  
DGG, DGV, OR DL PACKAGE  
(TOP VIEW)  
D
D
D
D
D
Member of the Texas Instruments  
WidebusFamily  
Typical V  
<0.8 V at V  
(Output Ground Bounce)  
OLP  
CC  
1
48  
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27  
26  
25  
1OE  
1Q1  
1Q2  
GND  
1Q3  
1Q4  
1LE  
1D1  
1D2  
GND  
1D3  
1D4  
= 3.3 V, T = 25°C  
A
2
Typical V  
(Output V  
Undershoot)  
3
OHV  
OH  
>2 V at V  
= 3.3 V, T = 25°C  
CC  
A
4
I
Supports Partial-Power-Down Mode  
5
off  
Operation  
6
7
V
V
Supports Mixed-Mode Signal Operation  
(5-V Input and Output Voltages With  
CC  
CC  
8
1Q5  
1Q6  
GND  
1Q7  
1Q8  
2Q1  
2Q2  
GND  
2Q3  
2Q4  
1D5  
1D6  
GND  
1D7  
1D8  
2D1  
2D2  
GND  
2D3  
2D4  
9
3.3-V V  
)
CC  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
D
Bus Hold on Data Inputs Eliminates the  
Need for External Pullup/Pulldown  
Resistors  
D
D
Latch-Up Performance Exceeds 250 mA Per  
JESD 17  
ESD Protection Exceeds JESD 22  
− 2000-V Human-Body Model (A114-A)  
− 200-V Machine Model (A115-A)  
V
V
CC  
CC  
2Q5  
2Q6  
GND  
2Q7  
2Q8  
2OE  
2D5  
2D6  
GND  
2D7  
2D8  
2LE  
description/ordering information  
This 16-bit transparent D-type latch is designed  
for 1.65-V to 3.6-V V  
operation.  
CC  
The SN74LVCH16373A is particularly suitable for  
implementing buffer registers, I/O ports,  
bidirectional bus drivers, and working registers. It  
can be used as two 8-bit latches or one 16-bit latch. When the latch-enable (LE) input is high, the Q outputs follow  
the data (D) inputs. When LE is taken low, the Q outputs are latched at the levels set up at the D inputs.  
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high  
or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive  
the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines  
without interface or pullup components.  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
†
PACKAGE  
T
A
Tube  
SN74LVCH16373ADL  
SSOP − DL  
LVCH16373A  
Tape and reel  
Tape and reel  
Tape and reel  
SN74LVCH16373ADLR  
SN74LVCH16373ADGGR  
SN74LVCH16373ADGVR  
SN74LVCH16373AGQLR  
SN74LVCH16373AZQLR  
TSSOP − DGG  
LVCH16373A  
LDH373A  
−40°C to 85°C  
TVSOP − DGV  
VFBGA − GQL  
Tape and reel  
LDH373A  
VFBGA − ZQL (Pb-free)  
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are  
available at www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Widebus is a trademark of Texas Instruments.  
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Copyright 2003, Texas Instruments Incorporated  
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...13

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