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SN74LVCC3245A-EP PDF预览

SN74LVCC3245A-EP

更新时间: 2024-11-15 12:47:03
品牌 Logo 应用领域
德州仪器 - TI 输出元件
页数 文件大小 规格书
19页 654K
描述
OCTAL BUS TRASCEIVER WITH ADJJUSTABLE OUTPUT VOLTAGE AND 3-STATE OUTPUTS

SN74LVCC3245A-EP 数据手册

 浏览型号SN74LVCC3245A-EP的Datasheet PDF文件第2页浏览型号SN74LVCC3245A-EP的Datasheet PDF文件第3页浏览型号SN74LVCC3245A-EP的Datasheet PDF文件第4页浏览型号SN74LVCC3245A-EP的Datasheet PDF文件第5页浏览型号SN74LVCC3245A-EP的Datasheet PDF文件第6页浏览型号SN74LVCC3245A-EP的Datasheet PDF文件第7页 
ꢎ ꢆꢏꢊꢄ ꢐꢑ ꢀ ꢏ ꢒꢊꢁꢀ ꢆꢌꢓ ꢅꢌꢒ ꢔ ꢓꢏ ꢕ ꢊꢖꢗ ꢑꢀ ꢏꢊꢐꢄ ꢌ ꢎ ꢑꢏ ꢍꢑꢏ ꢅ ꢎ ꢄꢏꢊ ꢘ  
ꢊꢁꢖ ꢇ ꢋꢀꢏꢊꢏ ꢌ ꢎ ꢑꢏ ꢍ ꢑꢏ  
SCAS773A − JUNE 2004 − REVISED MARCH 2005  
D
D
Controlled Baseline  
− One Assembly/Test Site, One Fabrication  
Site  
D
ESD Protection Exceeds JESD 22  
− 2000-V Human-Body Model (A114-A)  
− 200-V Machine Model (A115-A)  
− 1000-V Charged-Device Model (C101)  
Enhanced Diminishing Manufacturing  
Sources (DMS) Support  
DB, DW, OR PW PACKAGE  
(TOP VIEW)  
D
D
D
D
D
D
Enhanced Product-Change Notification  
Qualification Pedigree  
1
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
14  
13  
Bidirectional Voltage Translator  
V
V
CCB  
CCA  
DIR  
2
NC  
OE  
B1  
B2  
B3  
B4  
B5  
B6  
B7  
2.3 V to 3.6 V on A Port and 3 V to 5.5 V on  
B Port  
3
A1  
A2  
A3  
A4  
A5  
A6  
A7  
A8  
4
Control Inputs V /V Levels Are  
IH IL  
5
Referenced to V  
Voltage  
CCA  
6
Latch-Up Performance Exceeds 250 mA Per  
JESD 17  
7
8
Component qualification in accordance with JEDEC and industry  
standards to ensure reliable operation over an extended  
temperature range. This includes, but is not limited to, Highly  
Accelerated Stress Test (HAST) or biased 85/85, temperature  
cycle, autoclave or unbiased HAST, electromigration, bond  
intermetallic life, and mold compound life. Such qualification  
testing should not be viewed as justifying use of this component  
beyond specified performance and environmental limits.  
9
10  
11  
12  
GND  
GND  
B8  
GND  
NC − No internal connection  
description/ordering information  
This 8-bit (octal) noninverting bus transceiver contains two separate supply rails. The B port is designed to track  
, which accepts voltages from 3 V to 5.5 V, and the A port is designed to track V , which operates at  
V
CCB  
CCA  
2.3 V to 3.6 V. This allows for translation from a 3.3-V to a 5-V system environment and vice versa, from a 2.5-V  
to a 3.3-V system environment and vice versa.  
The SN74LVCC3245A is designed for asynchronous communication between data buses. The device  
transmits data from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the  
direction-control (DIR) input. The output-enable (OE) input can be used to disable the device so the buses are  
isolated. The control circuitry (DIR, OE) is powered by V  
.
CCA  
ORDERING INFORMATION  
ORDERABLE  
TOP-SIDE  
MARKING  
PACKAGE  
T
A
PART NUMBER  
CLVCC3245AIDWREP  
CLVCC3245AIDBREP  
CLVCC3245AIPWREP  
SOIC − DW  
SSOP − DB  
TSSOP − PW  
Reel of 2000  
Reel of 2000  
Reel of 2000  
LVCC3245A  
LH245AEP  
LH245AEP  
−40°C to 85°C  
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are  
available at www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
ꢏꢤ  
Copyright 2005, Texas Instruments Incorporated  
ꢠ ꢤ ꢡ ꢠꢙ ꢚꢮ ꢜꢛ ꢟ ꢧꢧ ꢥꢟ ꢝ ꢟ ꢞ ꢤ ꢠ ꢤ ꢝ ꢡ ꢩ  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

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