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SN74LVC841ADW PDF预览

SN74LVC841ADW

更新时间： 2024-02-27 16:41:27
品牌 Logo 应用领域
德州仪器 - TI 总线驱动器总线收发器锁存器逻辑集成电路光电二极管输出元件
页数 文件大小 规格书
9页 138K
描述
10-BIT BUS-INTERFACE D-TYPE LATCH WITH 3-STATE OUTPUTS

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SN74LVC841ADW 技术参数

是否无铅： 含铅是否Rohs认证： 不符合
生命周期：Obsolete包装说明：TSSOP, TSSOP24,.25
Reach Compliance Code：not_compliantHTS代码：8542.39.00.01
风险等级：5.36其他特性：TYP VOLP < 0.8V AT VCC = 3.3V, TA = 25 DEGREE C
系列：LVC/LCX/ZJESD-30 代码：R-PDSO-G24
长度：7.8 mm负载电容（CL）：50 pF
逻辑集成电路类型：BUS DRIVER最大I（ol）：0.024 A
位数：10功能数量：1
端口数量：2端子数量：24
最高工作温度：85 °C最低工作温度：-40 °C
输出特性：3-STATE输出极性：TRUE
封装主体材料：PLASTIC/EPOXY封装代码：TSSOP
封装等效代码：TSSOP24,.25封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH包装方法：TAPE AND REEL
峰值回流温度（摄氏度）：NOT SPECIFIED电源：3.3 V
Prop。Delay @ Nom-Sup：8 ns认证状态：Not Qualified
座面最大高度：1.2 mm子类别：FF/Latches
最大供电电压 (Vsup)：3.6 V最小供电电压 (Vsup)：2 V
标称供电电压 (Vsup)：3.3 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子形式：GULL WING端子节距：0.65 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：4.4 mmBase Number Matches：1

SN74LVC841ADW 数据手册

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SN74LVC841A  
10-BIT BUS-INTERFACE D-TYPE LATCH  
WITH 3-STATE OUTPUTS  
SCAS307H – MARCH 1993 – REVISED AUGUST 1998  
DB, DW, OR PW PACKAGE  
(TOP VIEW)  
EPIC (Enhanced-Performance Implanted  
CMOS) Submicron Process  
Typical V  
< 0.8 V at V  
(Output Ground Bounce)  
OLP  
OE  
1D  
2D  
3D  
4D  
5D  
6D  
7D  
8D  
1
2
3
4
5
6
7
8
9
24  
V
CC  
= 3.3 V, T = 25°C  
CC  
A
23 1Q  
22 2Q  
21 3Q  
20 4Q  
19 5Q  
18 6Q  
17 7Q  
16 8Q  
15 9Q  
14 10Q  
13 LE  
Typical V  
> 2 V at V  
(Output V  
Undershoot)  
OHV  
OH  
= 3.3 V, T = 25°C  
CC  
A
Power Off Disables Outputs, Permitting  
Live Insertion  
Supports Mixed-Mode Signal Operation on  
All Ports (5-V Input/Output Voltage With  
3.3-V V  
)
CC  
9D 10  
10D 11  
GND 12  
ESD Protection Exceeds 2000 V Per  
MIL-STD-883, Method 3015; Exceeds 200 V  
Using Machine Model (C = 200 pF, R = 0)  
Latch-Up Performance Exceeds 250 mA Per  
JESD 17  
Package Options Include Plastic  
Small-Outline (DW), Shrink Small-Outline  
(DB), and Thin Shrink Small-Outline (PW)  
Packages  
description  
This 10-bit bus-interface D-type latch is designed for 1.65-V to 3.6-V V  
operation.  
CC  
The SN74LVC841A is designed specifically for driving highly capacitive or relatively low-impedance loads. It  
is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and  
working registers.  
The ten latches are transparent D-type latches. The device has noninverting data (D) inputs and provides true  
data at its outputs.  
A buffered output-enable (OE) input can be used to place the ten outputs in either a normal logic state (high  
or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive  
thebuslinessignificantly. Thehigh-impedancestateandincreaseddriveprovidethecapabilitytodrivebuslines  
without interface or pullup components.  
OE does not affect the internal operations of the latch. Previously stored data can be retained or new data can  
be entered while the outputs are in the high-impedance state.  
Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators  
in a mixed 3.3-V/5-V system environment.  
To ensure the high-impedance state during power up or power down, OE should be tied to V through a pullup  
CC  
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.  
The SN74LVC841A is characterized for operation from –40°C to 85°C.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
EPIC is a trademark of Texas Instruments Incorporated.  
Copyright 1998, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...9

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SN74LVC841ADW 替代型号

型号 品牌 替代类型 描述 数据表
SN74LVC841APWR TI

完全替代

 10-BIT BUS-INTERFACE D-TYPE LATCH WITH 3-STATE OUTPUTS
SN74LVC827APW TI

完全替代

 10-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS
SN74LVC827ADW TI

完全替代

 10-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS

与SN74LVC841ADW相关器件

型号 品牌 获取价格 描述 数据表
SN74LVC841ADWE4 TI

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 		LVC/LCX/Z SERIES, 10-BIT DRIVER, TRUE OUTPUT, PDSO24, GREEN, PLASTIC, SOIC-24
SN74LVC841ADWG4 TI

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 		LVC/LCX/Z SERIES, 10-BIT DRIVER, TRUE OUTPUT, PDSO24, GREEN, PLASTIC, SOIC-24
SN74LVC841ADWR TI

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 		LVC/LCX/Z SERIES, 10-BIT DRIVER, TRUE OUTPUT, PDSO24, GREEN, PLASTIC, SOIC-24
SN74LVC841ADWRE4 TI

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 		IC LVC/LCX/Z SERIES, 10-BIT DRIVER, TRUE OUTPUT, PDSO24, GREEN, PLASTIC, SOIC-24, Bus Driv
SN74LVC841ADWRG4 TI

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 		LVC/LCX/Z SERIES, 10-BIT DRIVER, TRUE OUTPUT, PDSO24, GREEN, PLASTIC, SOIC-24
SN74LVC841APW TI

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 		10-BIT BUS-INTERFACE D-TYPE LATCH WITH 3-STATE OUTPUTS
SN74LVC841APWE4 TI

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 		10-Bit Bus-Interface D-Type Latch With 3-State Outputs 24-TSSOP -40 to 85
SN74LVC841APWG4 TI

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 		LVC/LCX/Z SERIES, 10-BIT DRIVER, TRUE OUTPUT, PDSO24, GREEN, PLASTIC, TSSOP-24
SN74LVC841APWLE TI

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 		10-Bit Bus-Interface D-Type Latch With 3-State Outputs 24-TSSOP -40 to 85
SN74LVC841APWR TI

获取价格

 		10-BIT BUS-INTERFACE D-TYPE LATCH WITH 3-STATE OUTPUTS

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