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SN74LVC828ADBLE PDF预览

SN74LVC828ADBLE

更新时间: 2024-01-24 09:24:37
品牌 Logo 应用领域
德州仪器 - TI 驱动器输出元件
页数 文件大小 规格书
8页 129K
描述
10-Bit Buffer/Driver With 3-State Outputs 24-SSOP -40 to 85

SN74LVC828ADBLE 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:TSSOP
包装说明:TSSOP, TSSOP24,.25针数:24
Reach Compliance Code:compliantHTS代码:8542.39.00.01
Factory Lead Time:1 week风险等级:5.37
其他特性:WITH DUAL OUTPUT ENABLE控制类型:ENABLE LOW
计数方向:UNIDIRECTIONAL系列:LVC/LCX/Z
JESD-30 代码:R-PDSO-G24JESD-609代码:e4
长度:7.8 mm负载电容(CL):50 pF
逻辑集成电路类型:BUS DRIVER最大I(ol):0.024 A
湿度敏感等级:1位数:10
功能数量:1端口数量:2
端子数量:24最高工作温度:85 °C
最低工作温度:-40 °C输出特性:3-STATE
输出极性:INVERTED封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装等效代码:TSSOP24,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
包装方法:TR峰值回流温度(摄氏度):260
电源:3.3 V最大电源电流(ICC):0.01 mA
Prop。Delay @ Nom-Sup:6.7 ns传播延迟(tpd):7.1 ns
认证状态:Not Qualified座面最大高度:1.2 mm
子类别:Bus Driver/Transceivers最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):1.65 V标称供电电压 (Vsup):1.8 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
翻译:N/A宽度:4.4 mm
Base Number Matches:1

SN74LVC828ADBLE 数据手册

 浏览型号SN74LVC828ADBLE的Datasheet PDF文件第2页浏览型号SN74LVC828ADBLE的Datasheet PDF文件第3页浏览型号SN74LVC828ADBLE的Datasheet PDF文件第4页浏览型号SN74LVC828ADBLE的Datasheet PDF文件第5页浏览型号SN74LVC828ADBLE的Datasheet PDF文件第6页浏览型号SN74LVC828ADBLE的Datasheet PDF文件第7页 
SN74LVC828A  
10-BIT BUFFER/DRIVER  
WITH 3-STATE OUTPUTS  
SCAS347E – MARCH 1994 – REVISED JUNE 1998  
DB, DW, OR PW PACKAGE  
(TOP VIEW)  
EPIC (Enhanced-Performance Implanted  
CMOS) Submicron Process  
Typical V  
< 0.8 V at V  
(Output Ground Bounce)  
OLP  
1
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
14  
13  
OE1  
A1  
A2  
A3  
A4  
A5  
A6  
A7  
A8  
V
CC  
= 3.3 V, T = 25°C  
CC  
A
2
Y1  
Y2  
Y3  
Y4  
Y5  
Y6  
Y7  
Y8  
Y9  
Y10  
OE2  
Typical V  
> 2 V at V  
(Output V  
Undershoot)  
3
OHV  
OH  
= 3.3 V, T = 25°C  
4
CC  
A
5
Supports Mixed-Mode Signal Operation on  
All Ports (5-V Input/Output Voltage With  
6
7
3.3-V V  
)
CC  
8
ESD Protection Exceeds 2000 V Per  
MIL-STD-883, Method 3015; Exceeds 200 V  
Using Machine Model (C = 200 pF, R = 0)  
9
10  
11  
12  
A9  
A10  
GND  
Latch-Up Performance Exceeds 250 mA Per  
JESD 17  
Package Options Include Plastic  
Small-Outline (DW), Shrink Small-Outline  
(DB), and Thin Shrink Small-Outline (PW)  
Packages  
description  
This 10-bit buffer/bus driver is designed for 1.65-V to 3.6-V V  
operation.  
CC  
The SN74LVC828A provides a high-performance bus interface for wide data paths or buses carrying parity.  
The 3-state control gate is a 2-input AND gate with active-low inputs so that if either output-enable (OE1 or OE2)  
input is high, all ten outputs are in the high-impedance state. The SN74LVC828A provides inverting data at  
its outputs.  
Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators  
in a mixed 3.3-V/5-V system environment.  
To ensure the high-impedance state during power up or power down, OE should be tied to V through a pullup  
CC  
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.  
The SN74LVC828A is characterized for operation from –40°C to 85°C.  
FUNCTION TABLE  
INPUTS  
OUTPUT  
Y
OE1  
L
OE2  
L
A
L
H
L
L
L
H
X
X
H
X
Z
Z
X
H
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
EPIC is a trademark of Texas Instruments Incorporated.  
Copyright 1998, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

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