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SN74LVC823ANSRG4 PDF预览

SN74LVC823ANSRG4

更新时间： 2024-09-30 15:52:23
品牌 Logo 应用领域
德州仪器 - TI 驱动光电二极管输出元件逻辑集成电路触发器
页数 文件大小 规格书
17页 640K
描述
IC LVC/LCX/Z SERIES, 9-BIT DRIVER, TRUE OUTPUT, PDSO24, GREEN, PLASTIC, SOP-24, Bus Driver/Transceiver

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SN74LVC823ANSRG4 技术参数

是否Rohs认证： 符合生命周期：Obsolete
零件包装代码：SOIC包装说明：SOP, SOP24,.3
针数：24Reach Compliance Code：compliant
风险等级：5.84其他特性：WITH CLEAR AND CLOCK ENABLE
系列：LVC/LCX/ZJESD-30 代码：R-PDSO-G24
长度：15 mm负载电容（CL）：50 pF
逻辑集成电路类型：BUS DRIVER最大频率@ Nom-Sup：150000000 Hz
最大I（ol）：0.024 A位数：9
功能数量：1端口数量：2
端子数量：24最高工作温度：85 °C
最低工作温度：-40 °C输出特性：3-STATE
输出极性：TRUE封装主体材料：PLASTIC/EPOXY
封装代码：SOP封装等效代码：SOP24,.3
封装形状：RECTANGULAR封装形式：SMALL OUTLINE
包装方法：TAPE AND REEL峰值回流温度（摄氏度）：NOT SPECIFIED
电源：3.3 VProp。Delay @ Nom-Sup：8 ns
传播延迟（tpd）：8.9 ns认证状态：Not Qualified
座面最大高度：2 mm子类别：FF/Latches
最大供电电压 (Vsup)：3.6 V最小供电电压 (Vsup)：1.65 V
标称供电电压 (Vsup)：1.8 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子形式：GULL WING端子节距：1.27 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
触发器类型：POSITIVE EDGE宽度：5.3 mm
Base Number Matches：1

SN74LVC823ANSRG4 数据手册

 浏览型号SN74LVC823ANSRG4的Datasheet PDF文件第2页浏览型号SN74LVC823ANSRG4的Datasheet PDF文件第3页浏览型号SN74LVC823ANSRG4的Datasheet PDF文件第4页浏览型号SN74LVC823ANSRG4的Datasheet PDF文件第5页浏览型号SN74LVC823ANSRG4的Datasheet PDF文件第6页浏览型号SN74LVC823ANSRG4的Datasheet PDF文件第7页 
SN74LVC823A  
9-BIT BUS-INTERFACE FLIP-FLOP  
WITH 3-STATE OUTPUTS  
www.ti.com  
SCAS305I–MARCH 1993–REVISED FEBRUARY 2005  
FEATURES  
DB, DGV, DW, NS, OR PW PACKAGE  
(TOP VIEW)  
•
•
•
•
Operates From 1.65 V to 3.6 V  
Inputs Accept Voltages to 5.5 V  
Max tpd of 7.9 ns at 3.3 V  
OE  
1D  
2D  
3D  
4D  
5D  
6D  
7D  
8D  
V
CC  
1
2
3
4
5
6
7
8
9
24  
23  
1Q  
Typical VOLP (Output Ground Bounce)  
22 2Q  
<0.8 V at VCC = 3.3 V, TA = 25°C  
3Q  
4Q  
5Q  
6Q  
21  
20  
19  
18  
•
•
Typical VOHV (Output VOH Undershoot)  
>2 V at VCC = 3.3 V, TA = 25°C  
Supports Mixed-Mode Signal Operation on All  
Ports (5-V Input/Output Voltage With  
17 7Q  
16 8Q  
15 9Q  
3.3-V VCC  
)
9D 10  
•
•
•
Ioff Supports Partial-Power-Down Mode  
Operation  
CLR  
GND  
CLKEN  
CLK  
11  
12  
14  
13  
Latch-Up Performance Exceeds 250 mA Per  
JESD 17  
ESD Protection Exceeds JESD 22  
– 2000-V Human-Body Model (A114-A)  
– 200-V Machine Model (A115-A)  
– 1000-V Charged-Device Model (C101)  
DESCRIPTION/ORDERING INFORMATION  
This 9-bit bus-interface flip-flop is designed for 1.65-V to 3.6-V VCC operation.  
The SN74LVC823A is designed specifically for driving highly capacitive or relatively low-impedance loads. It is  
particularly suitable for implementing wider buffer registers, I/O ports, bidirectional bus drivers with parity, and  
working registers.  
With the clock-enable (CLKEN) input low, the nine D-type edge-triggered flip-flops enter data on the low-to-high  
transitions of the clock. Taking CLKEN high disables the clock buffer, latching the outputs. This device has  
noninverting data (D) inputs. Taking the clear (CLR) input low causes the nine Q outputs to go low,  
independently of the clock.  
ORDERING INFORMATION  
TA  
PACKAGE(1)  
ORDERABLE PART NUMBER  
SN74LVC823ADW  
TOP-SIDE MARKING  
Tube of 25  
SOIC – DW  
LVC823A  
Reel of 2000  
Reel of 2000  
Reel of 2000  
Tube of 60  
SN74LVC823ADWR  
SN74LVC823ANSR  
SN74LVC823ADBR  
SN74LVC823APW  
SOP – NS  
LVC823A  
LC823A  
SSOP – DB  
–40°C to 85°C  
TSSOP – PW  
Reel of 2000  
Reel of 250  
Reel of 2000  
SN74LVC823APWR  
SN74LVC823APWT  
SN74LVC823ADGVR  
LC823A  
TVSOP – DGV  
LC823A  
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at  
www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
PRODUCTION DATA information is current as of publication date.  
Copyright © 1993–2005, Texas Instruments Incorporated  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
1234567...17

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