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SN74LVC652ANSR PDF预览

SN74LVC652ANSR

更新时间： 2024-11-17 13:13:51
品牌 Logo 应用领域
德州仪器 - TI 总线收发器输出元件
页数 文件大小 规格书
13页 198K
描述
LVC/LCX/Z SERIES, 8-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO24, GREEN, PLASTIC, SOP-24

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SN74LVC652ANSR 技术参数

是否Rohs认证： 符合生命周期：Obsolete
零件包装代码：SOIC包装说明：SOP, SOP24,.3
针数：24Reach Compliance Code：unknown
HTS代码：8542.39.00.01风险等级：5.75
其他特性：WITH INDEPENDENT OUTPUT ENABLE FOR EACH DIRECTION控制类型：INDEPENDENT CONTROL
计数方向：BIDIRECTIONAL系列：LVC/LCX/Z
JESD-30 代码：R-PDSO-G24长度：15 mm
逻辑集成电路类型：REGISTERED BUS TRANSCEIVER最大I（ol）：0.024 A
位数：8功能数量：1
端口数量：2端子数量：24
最高工作温度：85 °C最低工作温度：-40 °C
输出特性：3-STATE输出极性：TRUE
封装主体材料：PLASTIC/EPOXY封装代码：SOP
封装等效代码：SOP24,.3封装形状：RECTANGULAR
封装形式：SMALL OUTLINE包装方法：TAPE AND REEL
峰值回流温度（摄氏度）：NOT SPECIFIED电源：3.3 V
Prop。Delay @ Nom-Sup：7.4 ns传播延迟（tpd）：8.4 ns
认证状态：Not Qualified座面最大高度：2 mm
子类别：Bus Driver/Transceivers最大供电电压 (Vsup)：3.6 V
最小供电电压 (Vsup)：1.65 V标称供电电压 (Vsup)：1.8 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子形式：GULL WING
端子节距：1.27 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED翻译：N/A
触发器类型：POSITIVE EDGE宽度：5.3 mm
Base Number Matches：1

SN74LVC652ANSR 数据手册

 浏览型号SN74LVC652ANSR的Datasheet PDF文件第2页浏览型号SN74LVC652ANSR的Datasheet PDF文件第3页浏览型号SN74LVC652ANSR的Datasheet PDF文件第4页浏览型号SN74LVC652ANSR的Datasheet PDF文件第5页浏览型号SN74LVC652ANSR的Datasheet PDF文件第6页浏览型号SN74LVC652ANSR的Datasheet PDF文件第7页 
SN54LVC652A, SN74LVC652A  
OCTAL BUS TRANSCEIVERS AND REGISTERS  
WITH 3-STATE OUTPUTS  
SCAS303H – JANUARY 1993 – REVISED AUGUST 1998  
SN74LVC652A . . . DB, DW, OR PW PACKAGE  
(TOP VIEW)  
EPIC (Enhanced-Performance Implanted  
CMOS) Submicron Process  
Typical V  
< 0.8 V at V  
(Output Ground Bounce)  
OLP  
CLKAB  
SAB  
OEAB  
A1  
V
CC  
1
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
14  
= 3.3 V, T = 25°C  
CC  
A
CLKBA  
SBA  
OEBA  
B1  
2
Typical V  
> 2 V at V  
(Output V  
Undershoot)  
3
OHV  
OH  
= 3.3 V, T = 25°C  
4
CC  
A
A2  
5
Support Mixed-Mode Signal Operation on  
All Ports (5-V Input/Output Voltage With  
A3  
B2  
6
A4  
B3  
3.3-V V  
)
7
CC  
A5  
B4  
8
ESD Protection Exceeds 2000 V Per  
MIL-STD-883, Method 3015; Exceeds 200 V  
Using Machine Model (C = 200 pF, R = 0)  
A6  
B5  
9
A7  
B6  
10  
11  
A8  
B7  
Package Options Include Plastic  
GND 12  
13 B8  
Small-Outline (DW), Shrink Small-Outline  
(DB), Thin Shrink Small-Outline (PW)  
Packages, and Ceramic Chip Carriers (FK)  
SN54LVC652A . . . FK PACKAGE  
(TOP VIEW)  
description  
The SN54LVC652A octal bus transceiver and  
register is designed for 2.7-V to 3.6-V V  
CC  
operation, and the SN74LVC652A octal bus  
transceiver and register is designed for 1.65-V to  
4
3
2
1
28 27 26  
25  
5
6
7
8
9
A1  
A2  
A2  
NC  
A4  
OEBA  
B1  
B2  
NC  
B3  
B4  
24  
23  
22  
21  
20  
19  
3.6-V V  
operation.  
CC  
These devices consist of bus transceiver circuits,  
D-type flip-flops, and control circuitry arranged for  
multiplexed transmission of data directly from the  
data bus or from the internal storage registers.  
A5 10  
A6 11  
B5  
12 13 14 15 16 17 18  
Output-enable (OEAB and OEBA) inputs are  
provided to control the transceiver functions.  
Select-control (SAB and SBA) inputs are provided  
to select whether real-time or stored data is  
transferred. The circuitry used for select control  
eliminates the typical decoding glitch that occurs  
NC – No internal connection  
in a multiplexer during the transition between stored and real-time data. A low input selects real-time data, and  
a high input selects stored data. Figure 1 illustrates the four fundamental bus-management functions that are  
performed with the ’LVC652A.  
Data on the A or B data bus, or both, is stored in the internal D-type flip-flops by low-to-high transitions at the  
appropriate clock (CLKAB or CLKBA) inputs, regardless of the select- or enable-control pins. When SAB and  
SBA are in the real-time transfer mode, it is possible to store data without using the internal D-type flip-flops by  
simultaneously enabling OEAB and OEBA. In this configuration, each output reinforces its input. When all other  
data sources to the two sets of bus lines are at high impedance, each set of bus lines remains at its last state.  
Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators  
in a mixed 3.3-V/5-V system environment.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
EPIC is a trademark of Texas Instruments Incorporated.  
Copyright 1998, Texas Instruments Incorporated  
On products compliant to MIL-PRF-38535, all parameters are tested  
unless otherwise noted. On all other products, production  
processing does not necessarily include testing of all parameters.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...13

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