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SN74LVC646DW PDF预览

SN74LVC646DW

更新时间: 2024-11-18 23:06:23
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德州仪器 - TI 总线收发器输出元件
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描述
OCTAL BUS TRANSCEIVER AND REGISTER WITH 3-STATE OUTPUTS

SN74LVC646DW 数据手册

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SN74LVC646  
OCTAL BUS TRANSCEIVER AND REGISTER  
WITH 3-STATE OUTPUTS  
SCAS302A – JANUARY 1993 – REVISED JULY 1995  
DB, DW, OR PW PACKAGE  
(TOP VIEW)  
EPIC (Enhanced-Performance Implanted  
CMOS) Submicron Process  
Typical V  
< 0.8 V at V  
(Output Ground Bounce)  
OLP  
CLKAB  
SAB  
DIR  
A1  
A2  
A3  
A4  
A5  
A6  
A7  
A8  
GND  
V
CC  
1
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
14  
13  
= 3.3 V, T = 25°C  
CC  
A
CLKBA  
SBA  
OE  
B1  
B2  
B3  
B4  
B5  
B6  
B7  
2
Typical V  
> 2 V at V  
(Output V  
Undershoot)  
3
OHV  
OH  
= 3.3 V, T = 25°C  
4
CC  
A
5
Latch-Up Performance Exceeds 250 mA  
Per JEDEC Standard JESD-17  
6
7
Package Options Include Plastic  
Small-Outline (DW), Shrink Small-Outline  
(DB), and Thin Shrink Small-Outline (PW)  
Packages  
8
9
10  
11  
12  
description  
B8  
This octal bus transceiver and register is designed for 2.7-V to 3.6-V V  
operation.  
CC  
The SN74LVC646 consists of bus-transceiver circuits, D-type flip-flops, and control circuitry arranged for  
multiplexed transmission of data directly from the input bus or from the internal registers. Data on the A or B bus  
is clocked into the registers on the low-to-high transition of the appropriate clock (CLKAB or CLKBA) input.  
Figure 1 illustrates the four fundamental bus-management functions that can be performed with the  
SN74LVC646.  
Output-enable (OE) and direction-control (DIR) inputs control the transceiver functions. In the transceiver  
mode, data present at the high-impedance port can be stored in either register or in both.  
The select-control (SAB and SBA) inputs can multiplex stored and real-time (transparent mode) data. DIR  
determines which bus receives data when OE is low. In the isolation mode (OE high), A data can be stored in  
one register and B data can be stored in the other register.  
When an output function is disabled, the input function is still enabled and can be used to store and transmit  
data. Only one of the two buses, A or B, may be driven at a time.  
To ensure the high-impedance state during power up or power down, OE should be tied to V through a pullup  
CC  
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.  
The SN74LVC646 is characterized for operation from 40°C to 85°C.  
FUNCTION TABLE  
INPUTS  
DATA I/Os  
B1 – B8  
OPERATION OR FUNCTION  
OE  
X
X
H
H
L
DIR  
X
CLKAB  
CLKBA  
SAB  
X
SBA  
X
A1 – A8  
Input  
X
Unspecified  
Input  
Store A, B unspecified  
Store B, A unspecified  
Store A and B data  
X
X
X
X
Unspecified  
X
H or L  
X
H or L  
X
X
X
Input  
Input  
X
X
X
Input disabled  
Output  
Input disabled  
Input  
Isolation, hold storage  
Real-time B data to A bus  
Stored B data to A bus  
Real-time A data to B bus  
Stored A data to B bus  
L
X
L
L
L
X
H or L  
X
X
H
Output  
Input  
L
H
H
X
L
X
Input  
Output  
L
H or L  
X
H
X
Input  
Output  
The data output functions may be enabled or disabled by various signals at the OE and DIR inputs. Data input functions are always enabled;  
i.e., data at the bus pins is stored on every low-to-high transition of the clock inputs.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
EPIC is a trademark of Texas Instruments Incorporated.  
Copyright 1995, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

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