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SN74LVC646A

更新时间： 2024-11-20 23:06:23
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德州仪器 - TI 总线收发器输出元件
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13页 198K
描述
OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS

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SN74LVC646A 数据手册

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SN54LVC646A, SN74LVC646A  
OCTAL BUS TRANSCEIVERS AND REGISTERS  
WITH 3-STATE OUTPUTS  
SCAS302G – JANUARY 1993 – REVISED JUNE1998  
SN74LVC646A . . . DB, DW, OR PW PACKAGE  
(TOP VIEW)  
EPIC (Enhanced-Performance Implanted  
CMOS) Submicron Process  
Typical V  
< 0.8 V at V  
(Output Ground Bounce)  
OLP  
CLKAB  
SAB  
DIR  
A1  
A2  
A3  
A4  
A5  
A6  
A7  
A8  
GND  
V
CC  
1
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
14  
13  
= 3.3 V, T = 25°C  
CC  
A
CLKBA  
SBA  
OE  
B1  
B2  
B3  
B4  
B5  
B6  
B7  
2
Typical V  
> 2 V at V  
(Output V  
Undershoot)  
OHV  
OH  
3
= 3.3 V, T = 25°C  
CC  
A
4
Power Off Disables Outputs, Permitting  
Live Insertion  
5
6
7
Support Mixed-Mode Signal Operation on  
All Ports (5-V Input/Output Voltage With  
8
9
3.3-V V  
)
CC  
10  
11  
12  
ESD Protection Exceeds 2000 V Per  
MIL-STD-833, Method 3015; Exceeds 200 V  
Using Machine Model (C = 200 pF, R = 0)  
B8  
Latch-Up Performance Exceeds 250 mA Per  
JESD 17  
SN54LVC646A . . . FK PACKAGE  
(TOP VIEW)  
Package Options Include Plastic  
Small-Outline (DW), Shrink Small-Outline  
(DB), Thin Shrink Small-Outline (PW)  
Packages, and Ceramic Chip Carriers (FK)  
4
3
2
1
28 27 26  
25  
A1  
A2  
A3  
NC  
A4  
A5  
A6  
OE  
B1  
B2  
NC  
B3  
B4  
B5  
5
description  
24  
23  
22  
21  
20  
19  
6
The SN54LVC646A octal bus transceiver and  
7
register is designed for 2.7-V to 3.6-V V  
8
CC  
operation and the SN74LVC646A octal bus  
transceiver and register is designed for 1.65-V to  
9
10  
11  
3.6-V V  
operation.  
CC  
12 13 14 15 16 17 18  
These devices consist of bus-transceiver circuits,  
D-type flip-flops, and control circuitry arranged for  
multiplexed transmission of data directly from the  
input bus or from the internal registers. Data on  
the A or B bus is clocked into the registers on the  
low-to-high transition of the appropriate clock  
(CLKAB or CLKBA) input. Figure 1 illustrates the  
four fundamental bus-management functions that  
are performed with the ’LVC646A.  
NC – No internal connection  
Output-enable (OE) and direction-control (DIR) inputs control the transceiver functions. In the transceiver  
mode, data present at the high-impedance port is stored in either register or in both.  
The select-control (SAB and SBA) inputs can multiplex stored and real-time (transparent mode) data. DIR  
determines which bus receives data when OE is low. In the isolation mode (OE high), A data is stored in one  
register and B data can be stored in the other register.  
When an output function is disabled, the input function is still enabled and can be used to store and transmit  
data. Only one of the two buses, A or B, can be driven at a time.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
EPIC is a trademark of Texas Instruments Incorporated.  
Copyright 1998, Texas Instruments Incorporated  
On products compliant to MIL-PRF-38535, all parameters are tested  
unless otherwise noted. On all other products, production  
processing does not necessarily include testing of all parameters.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...13

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SN74LVC646A 替代型号

型号 品牌 替代类型 描述 数据表
SN54LVC646A TI

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