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SN74LVC574AQPWREP

更新时间： 2024-11-18 12:22:27
品牌 Logo 应用领域
德州仪器 - TI 总线驱动器总线收发器触发器逻辑集成电路光电二极管输出元件
页数 文件大小 规格书
9页 412K
描述
OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS

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中文翻译

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SN74LVC574AQPWREP 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：TSSOP
包装说明：TSSOP, TSSOP20,.25针数：20
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01Factory Lead Time：1 week
风险等级：0.99控制类型：INDEPENDENT CONTROL
计数方向：UNIDIRECTIONAL系列：LVC/LCX/Z
JESD-30 代码：R-PDSO-G20JESD-609代码：e4
长度：6.5 mm负载电容（CL）：50 pF
逻辑集成电路类型：BUS DRIVER最大频率@ Nom-Sup：150000000 Hz
最大I（ol）：0.024 A湿度敏感等级：1
位数：8功能数量：1
端口数量：2端子数量：20
最高工作温度：125 °C最低工作温度：-40 °C
输出特性：3-STATE输出极性：TRUE
封装主体材料：PLASTIC/EPOXY封装代码：TSSOP
封装等效代码：TSSOP20,.25封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH包装方法：TR
峰值回流温度（摄氏度）：260电源：3.3 V
最大电源电流（ICC）：0.01 mAProp。Delay @ Nom-Sup：7 ns
传播延迟（tpd）：8 ns认证状态：Not Qualified
座面最大高度：1.2 mm子类别：FF/Latches
最大供电电压 (Vsup)：3.6 V最小供电电压 (Vsup)：2 V
标称供电电压 (Vsup)：2.7 V表面贴装：YES
技术：CMOS温度等级：AUTOMOTIVE
端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)端子形式：GULL WING
端子节距：0.65 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED翻译：N/A
触发器类型：POSITIVE EDGE宽度：4.4 mm
Base Number Matches：1

SN74LVC574AQPWREP 数据手册

 浏览型号SN74LVC574AQPWREP的Datasheet PDF文件第2页浏览型号SN74LVC574AQPWREP的Datasheet PDF文件第3页浏览型号SN74LVC574AQPWREP的Datasheet PDF文件第4页浏览型号SN74LVC574AQPWREP的Datasheet PDF文件第5页浏览型号SN74LVC574AQPWREP的Datasheet PDF文件第6页浏览型号SN74LVC574AQPWREP的Datasheet PDF文件第7页 
SN74LVC574A-EP  
OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOP  
WITH 3-STATE OUTPUTS  
www.ti.com  
SCAS750A–DECEMBER 2003–REVISED AUGUST 2005  
FEATURES  
•
Controlled Baseline  
•
•
Supports Mixed-Mode Signal Operation on All  
Ports (5-V Input/Output Voltage With 3.3-V  
– One Assembly/Test Site, One Fabrication  
Site  
VCC  
)
Ioff Supports Partial-Power-Down Mode  
Operation  
•
•
Extended Temperature Performance of –40°C  
to 125°C  
Enhanced Diminishing Manufacturing  
Sources (DMS) Support  
DW OR PW PACKAGE  
(TOP VIEW)  
•
•
•
•
•
•
Enhanced Product-Change Notification  
(1)  
OE  
1D  
V
CC  
1
2
3
4
5
6
7
8
9
10  
20  
19  
Qualification Pedigree  
1Q  
Operates From 2 V to 3.6 V  
Inputs Accept Voltages to 5.5 V  
Max tpd of 7 ns at 3.3 V  
2D  
3D  
4D  
5D  
18 2Q  
17 3Q  
16  
15  
14  
13  
12  
11  
4Q  
5Q  
6Q  
7Q  
8Q  
CLK  
Typical VOLP (Output Ground Bounce) <0.8 V  
at VCC = 3.3 V, TA = 25°C  
6D  
•
Typical VOHV (Output VOH Undershoot) >2 V at  
VCC = 3.3 V, TA = 25°C  
7D  
8D  
GND  
(1) Component qualification in accordance with JEDEC and  
industry standards to ensure reliable operation over an  
extended temperature range. This includes, but is not limited  
to, Highly Accelerated Stress Test (HAST) or biased 85/85,  
temperature cycle, autoclave or unbiased HAST,  
electromigration, bond intermetallic life, and mold compound  
life. Such qualification testing should not be viewed as  
justifying use of this component beyond specified  
performance and environmental limits.  
DESCRIPTION/ORDERING INFORMATION  
The SN74LVC574A-EP octal edge-triggered D-type flip-flop is designed for 2.7-V to 3.6-V VCC operation.  
This device features 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance  
loads. It is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working  
registers.  
On the positive transition of the clock (CLK) input, the Q outputs are set to the logic levels at the data (D) inputs.  
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or  
low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the  
bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines  
without interface or pullup components.  
OE does not affect the internal operations of the flip-flops. Old data can be retained or new data can be entered  
while the outputs are in the high-impedance state.  
ORDERING INFORMATION  
TA  
PACKAGE(1)  
Reel of 2000  
Reel of 2000  
ORDERABLE PART NUMBER  
SN74LVC574AQDWREP  
TOP-SIDE MARKING  
C574AEP  
C574AEP  
SOIC – DW  
–40°C to 125°C  
TSSOP – PW  
SN74LVC574AQPWREP  
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at  
www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
PRODUCTION DATA information is current as of publication date.  
Copyright © 2003–2005, Texas Instruments Incorporated  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
1234567...9

中文翻译

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SN74LVC574AQPWREP 替代型号

型号 品牌 替代类型 描述 数据表
SN74LVC574AQPWRQ1 TI

类似代替

 OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS
CLVC574AQPWRG4Q1 TI

类似代替

 OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS

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