5秒后页面跳转
捷配首页

Datasheet > SN74LVC573A-Q1
SN74LVC573A-Q1 PDF预览

SN74LVC573A-Q1

更新时间： 2024-11-04 05:16:59
品牌 Logo 应用领域
德州仪器 - TI 锁存器
页数 文件大小 规格书
8页 192K
描述
OCTAL TRANSPARENT D-TYPE LATCH

阅读下载

中文翻译

获取价格

SN74LVC573A-Q1 数据手册

 浏览型号SN74LVC573A-Q1的Datasheet PDF文件第2页浏览型号SN74LVC573A-Q1的Datasheet PDF文件第3页浏览型号SN74LVC573A-Q1的Datasheet PDF文件第4页浏览型号SN74LVC573A-Q1的Datasheet PDF文件第5页浏览型号SN74LVC573A-Q1的Datasheet PDF文件第6页浏览型号SN74LVC573A-Q1的Datasheet PDF文件第7页 
ꢀꢁꢂ ꢃ ꢄꢅ ꢆꢇ ꢂꢈ ꢉꢊ ꢋ ꢌ  
ꢍ ꢆꢎꢉꢄ ꢎ ꢏꢉꢁꢀ ꢐꢉꢏꢑ ꢁꢎ ꢒꢊꢎ ꢓꢐꢑ ꢄꢉꢎꢆ ꢔ  
ꢕ ꢖꢎ ꢔ ꢈ ꢊꢀꢎꢉꢎ ꢑ ꢍ ꢗꢎ ꢐ ꢗꢎꢀ  
SCAS714A − SEPTEMBER 2003 − REVISED MAY 2004  
D
Qualification in Accordance With  
AEC-Q100  
D
D
Supports Mixed-Mode Signal Operation on  
All Ports (5-V Input/Output Voltage With  
†
3.3-V V  
)
CC  
D
Qualified for Automotive Applications  
I
Supports Partial-Power-Down Mode  
off  
D
Customer-Specific Configuration Control  
Can Be Supported Along With  
Major-Change Approval  
Operation  
DW OR PW PACKAGE  
(TOP VIEW)  
D
ESD Protection Exceeds 2000 V Per  
MIL-STD-883, Method 3015; Exceeds 200 V  
Using Machine Model (C = 200 pF, R = 0)  
1
2
3
4
5
6
7
8
9
10  
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
OE  
1D  
2D  
3D  
4D  
5D  
6D  
7D  
8D  
V
CC  
1Q  
2Q  
3Q  
4Q  
5Q  
6Q  
7Q  
8Q  
LE  
D
D
D
D
Operates From 2 V to 3.6 V  
Inputs Accept Voltages to 5.5 V  
Max t of 6.9 ns at 3.3 V  
pd  
Typical V  
<0.8 V at V  
(Output Ground Bounce)  
OLP  
CC  
= 3.3 V, T = 25°C  
A
D
Typical V  
(Output V  
Undershoot)  
OHV  
OH  
>2 V at V  
= 3.3 V, T = 25°C  
CC  
A
GND  
†
Contact factory for details. Q100 qualification data available on  
request.  
description/ordering information  
The SN74LVC573A octal transparent D-type latch is designed for 2.7-V to 3.6-V V  
operation.  
CC  
This device features 3-state outputs designed specifically for driving highly capacitive or relatively  
low-impedance loads. It is particularly suitable for implementing buffer registers, input/output (I/O) ports,  
bidirectional bus drivers, and working registers.  
While the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the  
Q outputs are latched at the logic levels at the D inputs.  
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high  
or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive  
the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus  
lines without interface or pullup components.  
OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered  
while the outputs are in the high-impedance state.  
This device is fully specified for partial-power-down applications using I . The I circuitry disables the outputs,  
off  
off  
preventing damaging current backflow through the device when it is powered down.  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
‡
PACKAGE  
T
A
SOIC − DW  
Reel of 2000  
Reel of 2000  
SN74LVC573AQDWRQ1  
SN74LVC573AQPWRQ1  
L573AQ1  
L573AQ1  
−40°C to 125°C  
TSSOP − PW  
‡
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are  
available at www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
ꢐ
ꢐ
ꢏ
ꢍ
ꢧ
ꢒ
ꢢ
ꢗ
ꢆ
ꢠ
ꢎ
ꢡ
ꢖ
ꢛ
ꢍ
ꢙ
ꢁ
ꢚ
ꢒ
ꢉ
ꢎ
ꢉ
ꢘ
ꢙ
ꢣ
ꢚ
ꢛ
ꢡ
ꢜ
ꢝ
ꢞ
ꢞ
ꢟ
ꢟ
ꢘ
ꢘ
ꢛ
ꢛ
ꢙ
ꢙ
ꢘ
ꢠ
ꢠ
ꢤ
ꢡ
ꢢ
ꢜ
ꢜ
ꢣ
ꢣ
ꢙ
ꢟ
ꢞ
ꢝ
ꢠ
ꢠ
ꢛ
ꢚ
ꢤ
ꢎꢣ  
ꢢ
ꢥ
ꢠ
ꢦ
ꢘ
ꢡ
ꢞ
ꢠ
ꢟ
ꢘ
ꢟ
ꢛ
ꢜ
ꢙ
ꢢ
ꢧ
ꢞ
ꢙ
ꢟ
ꢟ
ꢣ
ꢠ
ꢨ
Copyright 2004, Texas Instruments Incorporated  
ꢜ
ꢛ
ꢡ
ꢟ
ꢛ
ꢜ
ꢝ
ꢟ
ꢛ
ꢠ
ꢤ
ꢘ
ꢚ
ꢘ
ꢡ
ꢣ
ꢜ
ꢟ
ꢩ
ꢟ
ꢣ
ꢜ
ꢛ
ꢚ
ꢪ
ꢞ
ꢖ
ꢙ
ꢝ
ꢣ
ꢠ
ꢟ
ꢞ
ꢙ
ꢧ
ꢞ
ꢜ
ꢧ
ꢫ
ꢞ
ꢟ ꢣ ꢠ ꢟꢘ ꢙꢭ ꢛꢚ ꢞ ꢦꢦ ꢤꢞ ꢜ ꢞ ꢝ ꢣ ꢟ ꢣ ꢜ ꢠ ꢨ  
ꢜ
ꢜ
ꢞ
ꢙ
ꢟ
ꢬ
ꢨ
ꢐ
ꢜ
ꢛ
ꢧ
ꢢ
ꢡ
ꢟ
ꢘ
ꢛ
ꢙ
ꢤ
ꢜ
ꢛ
ꢡ
ꢣ
ꢠ
ꢠ
ꢘ
ꢙ
ꢭ
ꢧ
ꢛ
ꢣ
ꢠ
ꢙ
ꢛ
ꢟ
ꢙ
ꢣ
ꢡ
ꢣ
ꢠ
ꢠ
ꢞ
ꢜ
ꢘ
ꢦ
ꢬ
ꢘ
ꢙ
ꢡ
ꢦ
ꢢ
ꢧ
ꢣ
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
12345678

中文翻译

下载PDF

与SN74LVC573A-Q1相关器件

型号 品牌 获取价格 描述 数据表
SN74LVC573A-Q1_15 TI

获取价格

 		OCTAL TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS
SN74LVC573AQDWREP TI

获取价格

 		OCTAL TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS
SN74LVC573AQDWRQ1 TI

获取价格

 		OCTAL TRANSPARENT D-TYPE LATCH
SN74LVC573AQPWREP TI

获取价格

 		OCTAL TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS
SN74LVC573AQPWRQ1 TI

获取价格

 		OCTAL TRANSPARENT D-TYPE LATCH
SN74LVC573ARGYR TI

获取价格

 		OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS
SN74LVC573ARGYRG4 TI

获取价格

 		OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS
SN74LVC573AZQNR TI

获取价格

 		OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS
SN74LVC573DBR TI

获取价格

 		LVC/LCX/Z SERIES, 8-BIT DRIVER, TRUE OUTPUT, PDSO20, SSOP-20
SN74LVC574 TI

获取价格

 		OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS

与SN74LVC573A-Q1相关文章

您还可以找


热门产品
PCB打样/小批量
铝基板
BOM智能配单
PCBA制造
钣金
精密CNC
模具注塑
薄膜开关
精选活动
PCBA打样特惠
四六层板品质升级
铝基板品质升级
一体化电子制造
DFM下载
服务支持
企业认证
产品展示
工厂展示
工艺能力
积分商城
关于捷配
捷配简介
企业文化
公司动态
人才招聘
联系我们
帮助中心
下单流程
付款流程
开票流程
常见问题
全球PCB制造服务专线 400-613-0088

工作时间：9:00-21:00

CEO邮箱：ceo@jiepei.com

投诉邮箱：tousu@jiepei.com

捷配网-微信公众号 微信公众号
捷配网-微信公众号 抖音公众号
资质认证：
合作快递：
支付方式：
Copyright © 2024 Jiepei.com Inc. All Rights Reserved. 版权所有:杭州捷配信息科技有限公司 浙公网安备 33010502006866号 浙ICP备10014259号-119 营业执照ICP证