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SN74LVC4245A-EP PDF预览

SN74LVC4245A-EP

更新时间: 2024-01-18 18:17:39
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德州仪器 - TI 总线收发器输出元件
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13页 202K
描述
OCTAL BUS TRANSCEIVER AND 3.3-V TO 5-V SHIFTER WITH 3-STATE OUTPUTS

SN74LVC4245A-EP 数据手册

 浏览型号SN74LVC4245A-EP的Datasheet PDF文件第2页浏览型号SN74LVC4245A-EP的Datasheet PDF文件第3页浏览型号SN74LVC4245A-EP的Datasheet PDF文件第4页浏览型号SN74LVC4245A-EP的Datasheet PDF文件第5页浏览型号SN74LVC4245A-EP的Datasheet PDF文件第6页浏览型号SN74LVC4245A-EP的Datasheet PDF文件第7页 
ꢀꢁꢂ ꢃ ꢄꢅꢆꢃ ꢇꢃ ꢈꢉ ꢊꢋ ꢌ  
ꢍ ꢆꢎꢉꢄ ꢏꢐꢀ ꢎ ꢑꢉꢁꢀ ꢆꢋꢒ ꢅꢋꢑ ꢉꢁꢓ ꢔ ꢕꢔ ꢊꢅ ꢎ ꢍ ꢈ ꢊꢅ ꢀ ꢖꢒ ꢗꢎ ꢋꢑ  
ꢘ ꢒꢎ ꢖ ꢔ ꢊꢀꢎꢉꢎ ꢋ ꢍ ꢐꢎ ꢌ ꢐꢎꢀ  
SCAS742 − DECEMBER 2003  
D
D
D
D
D
D
D
Controlled Baseline  
− One Assembly/Test Site, One Fabrication  
Site  
D
ESD Protection Exceeds JESD 22  
− 2000-V Human-Body Model (A114-A)  
− 200-V Machine Model (A115-A)  
− 1000-V Charged-Device Model (C101)  
Enhanced Diminishing Manufacturing  
Sources (DMS) Support  
PW PACKAGE  
(TOP VIEW)  
Enhanced Product-Change Notification  
Qualification Pedigree  
1
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
14  
13  
(5 V) V  
V
V
(3.3 V)  
(3.3 V)  
CCA  
DIR  
CCB  
CCB  
2
Bidirectional Voltage Translator  
3
A1  
A2  
A3  
A4  
A5  
A6  
A7  
A8  
OE  
B1  
B2  
B3  
B4  
B5  
B6  
B7  
B8  
GND  
5.5 V on A Port and 2.7 V to 3.6 V on B Port  
4
Latch-Up Performance Exceeds 250 mA Per  
JESD 17  
5
6
Component qualification in accordance with JEDEC and industry  
standards to ensure reliable operation over an extended  
temperature range. This includes, but is not limited to, Highly  
Accelerated Stress Test (HAST) or biased 85/85, temperature  
cycle, autoclave or unbiased HAST, electromigration, bond  
intermetallic life, and mold compound life. Such qualification  
testing should not be viewed as justifying use of this component  
beyond specified performance and environmental limits.  
7
8
9
10  
11  
12  
GND  
GND  
description/ordering information  
This 8-bit (octal) noninverting bus transceiver contains two separate supply rails; B port has V  
, which is set  
CCB  
at 3.3 V, and A port has V  
and vice versa.  
, which is set at 5 V. This allows for translation from a 3.3-V to a 5-V environment,  
CCA  
The SN74LVC4245A is designed for asynchronous communication between data buses. The device transmits  
data from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the  
direction-control (DIR) input. The output-enable (OE) input can be used to disable the device so the buses are  
effectively isolated.  
The SN74LVC4245A pinout allows the designer to switch to a normal all-3.3-V or all-5-V 20-pin ’245 device  
without board re-layout. The designer uses the data paths for pins 211 and 1423 of the SN74LVC4245A to  
align with the conventional ’245 pinout.  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
T
A
PACKAGE  
−40°C to 85°C TSSOP − PW Reel of 2000  
SN74LVC4245AIPWREP  
C4245AEP  
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design  
guidelines are available at www.ti.com/sc/package.  
FUNCTION TABLE  
INPUTS  
OPERATION  
OE  
L
DIR  
L
B data to A bus  
A data to B bus  
Isolation  
L
H
H
X
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
ꢎꢤ  
Copyright 2003, Texas Instruments Incorporated  
ꢠ ꢤ ꢡ ꢠꢙ ꢚꢭ ꢜꢛ ꢟ ꢧꢧ ꢥꢟ ꢝ ꢟ ꢞ ꢤ ꢠ ꢤ ꢝ ꢡ ꢕ  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

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