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SN74LVC374ADWR PDF预览

SN74LVC374ADWR

更新时间： 2024-11-18 05:17:03
品牌 Logo 应用领域
德州仪器 - TI 总线驱动器总线收发器触发器逻辑集成电路光电二极管输出元件
页数 文件大小 规格书
21页 628K
描述
OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS

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中文翻译

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SN74LVC374ADWR 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：SOIC
包装说明：SOP, SOP20,.4针数：20
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01Factory Lead Time：1 week
风险等级：0.96控制类型：ENABLE LOW
计数方向：UNIDIRECTIONAL系列：LVC/LCX/Z
JESD-30 代码：R-PDSO-G20JESD-609代码：e4
长度：12.8 mm负载电容（CL）：50 pF
逻辑集成电路类型：BUS DRIVER最大频率@ Nom-Sup：100000000 Hz
最大I（ol）：0.024 A湿度敏感等级：1
位数：8功能数量：1
端口数量：2端子数量：20
最高工作温度：85 °C最低工作温度：-40 °C
输出特性：3-STATE输出极性：TRUE
封装主体材料：PLASTIC/EPOXY封装代码：SOP
封装等效代码：SOP20,.4封装形状：RECTANGULAR
封装形式：SMALL OUTLINE包装方法：TR
峰值回流温度（摄氏度）：260电源：3.3 V
最大电源电流（ICC）：0.01 mAProp。Delay @ Nom-Sup：7 ns
传播延迟（tpd）：8.1 ns认证状态：Not Qualified
座面最大高度：2.65 mm子类别：FF/Latches
最大供电电压 (Vsup)：3.6 V最小供电电压 (Vsup)：1.65 V
标称供电电压 (Vsup)：1.8 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)端子形式：GULL WING
端子节距：1.27 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED触发器类型：POSITIVE EDGE
宽度：7.5 mmBase Number Matches：1

SN74LVC374ADWR 数据手册

 浏览型号SN74LVC374ADWR的Datasheet PDF文件第2页浏览型号SN74LVC374ADWR的Datasheet PDF文件第3页浏览型号SN74LVC374ADWR的Datasheet PDF文件第4页浏览型号SN74LVC374ADWR的Datasheet PDF文件第5页浏览型号SN74LVC374ADWR的Datasheet PDF文件第6页浏览型号SN74LVC374ADWR的Datasheet PDF文件第7页 
SN54LVC374A, SN74LVC374A  
OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS  
WITH 3-STATE OUTPUTS  
www.ti.com  
SCAS296N–JANUARY 1993–REVISED MAY 2005  
FEATURES  
•
•
•
Ioff Supports Partial-Power-Down Mode  
Operation  
•
•
•
•
Operate From 1.65 V to 3.6 V  
Inputs Accept Voltages to 5.5 V  
Max tpd of 6.5 ns at 3.3 V  
Latch-Up Performance Exceeds 250 mA Per  
JESD 17  
ESD Protection Exceeds JESD 22  
– 2000-V Human-Body Model (A114-A)  
– 200-V Machine Model (A115-A)  
Typical VOLP (Output Ground Bounce)  
<0.8 V at VCC = 3.3 V, TA = 25°C  
•
•
Typical VOHV (Output VOH Undershoot)  
>2 V at VCC = 3.3 V, TA = 25°C  
– 1000-V Charged-Device Model (C101)  
Support Mixed-Mode Signal Operation on  
All Ports (5-V Input/Output Voltage  
With 3.3-V VCC  
)
SN54LVC374A . . . J OR W PACKAGE  
SN74LVC374A . . . DB, DGV, DW, N, NS,  
OR PW PACKAGE  
SN54LVC374A . . . FK PACKAGE  
(TOP VIEW)  
SN74LVC374A . . . RGY PACKAGE  
(TOP VIEW)  
(TOP VIEW)  
1
20  
OE  
1Q  
1D  
2D  
2Q  
3Q  
3D  
4D  
4Q  
V
3
2
1
20 19  
18  
1
2
3
4
5
6
7
8
9
20  
19  
18  
17  
16  
15  
CC  
8D  
7D  
7Q  
6Q  
6D  
2D  
4
5
6
7
8
19  
18  
17  
16  
15  
14  
13  
12  
2
3
4
5
6
7
8
9
1Q  
1D  
2D  
2Q  
3Q  
3D  
4D  
4Q  
8Q  
8D  
7D  
7Q  
6Q  
6D  
5D  
5Q  
8Q  
8D  
7D  
7Q  
6Q  
17  
16  
15  
14  
2Q  
3Q  
3D  
4D  
9 10 11 12 13  
14 6D  
13 5D  
12 5Q  
11 CLK  
10  
11  
GND 10  
DESCRIPTION/ORDERING INFORMATION  
The SN54LVC374A octal edge-triggered D-type flip-flop is designed for 2.7-V to 3.6-V VCC operation, and the  
SN74LVC374A octal edge-triggered D-type flip-flop is designed for 1.65-V to 3.6-V VCC operation.  
These devices feature 3-state outputs designed specifically for driving highly capacitive or relatively  
low-impedance loads. These devices are particularly suitable for implementing buffer registers, input/output (I/O)  
ports, bidirectional bus drivers, and working registers.  
On the positive transition of the clock (CLK) input, the Q outputs are set to the logic levels set up at the data (D)  
inputs.  
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or  
low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the  
bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines  
without interface or pullup components.  
OE does not affect internal operations of the latch. Old data can be retained or new data can be entered while  
the outputs are in the high-impedance state.  
Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators  
in a mixed 3.3-V/5-V system environment.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
PRODUCTION DATA information is current as of publication date.  
Copyright © 1993–2005, Texas Instruments Incorporated  
Products conform to specifications per the terms of the Texas  
On products compliant to MIL-PRF-38535, all parameters are  
Instruments standard warranty. Production processing does not  
tested unless otherwise noted. On all other products, production  
necessarily include testing of all parameters.  
processing does not necessarily include testing of all parameters.  
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中文翻译

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SN74LVC374ADWR 替代型号

型号 品牌 替代类型 描述 数据表
SN74LVC374ADWRE4 TI

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 OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS
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 OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS
SN74LVC374ADW TI

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