SN74LVC374A-Q1
OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOP
WITH 3-STATE OUTPUTS
www.ti.com
SCAS711B–SEPTEMBER 2003–REVISED FEBRUARY 2008
1
FEATURES
•
Qualified for Automotive Applications
DW OR PW PACKAGE
(TOP VIEW)
•
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
OE
1Q
1D
1
2
3
4
5
6
7
8
9
10
20 VCC
19
18
17
16
15
14
13
12
11
8Q
8D
7D
7Q
6Q
6D
5D
5Q
CLK
•
•
•
•
Operates From 2 V to 3.6 V
Inputs Accept Voltages to 5.5 V
Max tpd of 8.5 ns at 3.3 V
2D
2Q
Typical VOLP (Output Ground Bounce) < 0.8 V
at VCC = 3.3 V, TA = 25°C
3Q
3D
4D
•
•
•
Typical VOHV (Output VOH Undershoot) > 2 V
at VCC = 3.3 V, TA = 25°C
4Q
GND
Supports Mixed-Mode Signal Operation on All
Ports (5-V Input/Output Voltage With 3.3-V VCC
)
Ioff Supports Partial-Power-Down Mode
Operation
DESCRIPTION/ORDERING INFORMATION
The SN74LVC374A octal edge-triggered D-type flip-flop is designed for 2.7-V to 3.6-V VCC operation.
This device features 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance
loads. This device is particularly suitable for implementing buffer registers, input/output (I/O) ports, bidirectional
bus drivers, and working registers.
On the positive transition of the clock (CLK) input, the Q outputs are set to the logic levels set up at the data (D)
inputs.
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or
low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the
bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines
without interface or pullup components.
OE does not affect internal operations of the latch. Old data can be retained or new data can be entered while
the outputs are in the high-impedance state.
Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of this device as a translator in
a mixed 3.3-V/5-V system environment.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
ORDERING INFORMATION(1)
TA
PACKAGE(2)
Reel of 2000
Reel of 2000
ORDERABLE PART NUMBER
SN74LVC374AQDWRQ1
TOP-SIDE MARKING
L374AQ1
L374AQ1
SOIC – DW
–40°C to 125°C
TSSOP – PW
SN74LVC374AQPWRQ1
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2003–2008, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.