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SN74LVC373AQPWRQ1 PDF预览

SN74LVC373AQPWRQ1

更新时间： 2024-11-18 12:22:31
品牌 Logo 应用领域
德州仪器 - TI 总线驱动器总线收发器锁存器逻辑集成电路光电二极管输出元件
页数 文件大小 规格书
11页 224K
描述
OCTAL TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS

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SN74LVC373AQPWRQ1 技术参数

是否无铅： 含铅是否Rohs认证： 符合
生命周期：Obsolete零件包装代码：TSSOP
包装说明：TSSOP, TSSOP20,.25针数：20
Reach Compliance Code：unknownHTS代码：8542.39.00.01
风险等级：5.28系列：LVC/LCX/Z
JESD-30 代码：R-PDSO-G20长度：6.5 mm
负载电容（CL）：50 pF逻辑集成电路类型：BUS DRIVER
位数：8功能数量：1
端口数量：2端子数量：20
最高工作温度：125 °C最低工作温度：-40 °C
输出特性：3-STATE输出极性：TRUE
封装主体材料：PLASTIC/EPOXY封装代码：TSSOP
封装等效代码：TSSOP20,.25封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH包装方法：TR
峰值回流温度（摄氏度）：NOT SPECIFIED电源：3.3 V
Prop。Delay @ Nom-Sup：7.5 ns传播延迟（tpd）：9.5 ns
认证状态：Not Qualified筛选级别：AEC-Q100
座面最大高度：1.2 mm子类别：FF/Latches
最大供电电压 (Vsup)：3.6 V最小供电电压 (Vsup)：2 V
标称供电电压 (Vsup)：2.7 V表面贴装：YES
技术：CMOS温度等级：AUTOMOTIVE
端子形式：GULL WING端子节距：0.65 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：4.4 mmBase Number Matches：1

SN74LVC373AQPWRQ1 数据手册

 浏览型号SN74LVC373AQPWRQ1的Datasheet PDF文件第2页浏览型号SN74LVC373AQPWRQ1的Datasheet PDF文件第3页浏览型号SN74LVC373AQPWRQ1的Datasheet PDF文件第4页浏览型号SN74LVC373AQPWRQ1的Datasheet PDF文件第5页浏览型号SN74LVC373AQPWRQ1的Datasheet PDF文件第6页浏览型号SN74LVC373AQPWRQ1的Datasheet PDF文件第7页 
SN74LVC373A-Q1  
OCTAL TRANSPARENT D-TYPE LATCH  
WITH 3-STATE OUTPUTS  
www.ti.com  
SCAS710B–SEPTEMBER 2003–REVISED FEBRUARY 2008  
1
FEATURES  
•
Qualified for Automotive Applications  
DW OR PW PACKAGE  
(TOP VIEW)  
•
ESD Protection Exceeds 2000 V Per  
MIL-STD-883, Method 3015; Exceeds 200 V  
Using Machine Model (C = 200 pF, R = 0)  
OE  
1Q  
1D  
VCC  
1
2
3
4
5
6
7
8
9
10  
20  
19 8Q  
18 8D  
17 7D  
16 7Q  
•
•
•
•
Operates From 2 V to 3.6 V  
Inputs Accept Voltages to 5.5 V  
Max tpd of 7.5 ns at 3.3 V  
2D  
2Q  
Typical VOLP (Output Ground Bounce) < 0.8 V  
at VCC = 3.3 V, TA = 25°C  
15  
14  
13  
12  
11  
3Q  
6Q  
6D  
5D  
5Q  
LE  
3D  
4D  
•
•
•
Typical VOHV (Output VOH Undershoot) > 2 V  
at VCC = 3.3 V, TA = 25°C  
4Q  
GND  
Supports Mixed-Mode Signal Operation on All  
Ports (5-V Input/Output Voltage With 3.3-V VCC  
)
Ioff Supports Partial-Power-Down Mode  
Operation  
DESCRIPTION/ORDERING INFORMATION  
The SN74LVC373A octal transparent D-type latch is designed for 2.7-V to 3.6-V VCC operation.  
While the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q  
outputs are latched at the logic levels set up at the D inputs.  
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or  
low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the  
bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines  
without interface or pullup components.  
OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered  
while the outputs are in the high-impedance state.  
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,  
preventing damaging current backflow through the device when it is powered down.  
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup  
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.  
Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of this device as a translator in  
a mixed 3.3-V/5-V system environment.  
ORDERING INFORMATION(1)  
TA  
PACKAGE(2)  
Reel of 2000  
Reel of 2000  
ORDERABLE PART NUMBER  
SN74LVC373AQDWRQ1  
TOP-SIDE MARKING  
L373AQ1  
L373AQ1  
SOIC – DW  
–40°C to 125°C  
TSSOP – PW  
SN74LVC373AQPWRQ1  
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI  
web site at www.ti.com.  
(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.  
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
PRODUCTION DATA information is current as of publication date.  
Copyright © 2003–2008, Texas Instruments Incorporated  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
1234567...11

中文翻译

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SN74LVC373AQPWRQ1 替代型号

型号 品牌 替代类型 描述 数据表
SN74LVC373AQPWREP TI

完全替代

 OCTAL TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS
V62/04662-01YE TI

完全替代

 OCTAL TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS
CLVC373AQPWRG4Q1 TI

类似代替

 OCTAL TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS

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