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SN74LVC373ANSR PDF预览

SN74LVC373ANSR

更新时间： 2024-11-04 05:17:03
品牌 Logo 应用领域
德州仪器 - TI 锁存器输出元件
页数 文件大小 规格书
22页 757K
描述
OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS

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SN74LVC373ANSR 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：SOIC
包装说明：SOP, SOP20,.3针数：20
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01Factory Lead Time：6 weeks
风险等级：0.85控制类型：ENABLE LOW
计数方向：UNIDIRECTIONAL系列：LVC/LCX/Z
JESD-30 代码：R-PDSO-G20JESD-609代码：e4
长度：12.6 mm负载电容（CL）：50 pF
逻辑集成电路类型：BUS DRIVER最大I（ol）：0.024 A
湿度敏感等级：1位数：8
功能数量：1端口数量：2
端子数量：20最高工作温度：85 °C
最低工作温度：-40 °C输出特性：3-STATE
输出极性：TRUE封装主体材料：PLASTIC/EPOXY
封装代码：SOP封装等效代码：SOP20,.3
封装形状：RECTANGULAR封装形式：SMALL OUTLINE
包装方法：TR峰值回流温度（摄氏度）：260
电源：3.3 V最大电源电流（ICC）：0.01 mA
Prop。Delay @ Nom-Sup：6.8 ns传播延迟（tpd）：8.2 ns
认证状态：Not Qualified座面最大高度：2 mm
子类别：FF/Latches最大供电电压 (Vsup)：3.6 V
最小供电电压 (Vsup)：1.65 V标称供电电压 (Vsup)：1.8 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：GULL WING端子节距：1.27 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：5.3 mmBase Number Matches：1

SN74LVC373ANSR 数据手册

 浏览型号SN74LVC373ANSR的Datasheet PDF文件第2页浏览型号SN74LVC373ANSR的Datasheet PDF文件第3页浏览型号SN74LVC373ANSR的Datasheet PDF文件第4页浏览型号SN74LVC373ANSR的Datasheet PDF文件第5页浏览型号SN74LVC373ANSR的Datasheet PDF文件第6页浏览型号SN74LVC373ANSR的Datasheet PDF文件第7页 
SN54LVC373A, SN74LVC373A  
OCTAL TRANSPARENT D-TYPE LATCHES  
WITH 3-STATE OUTPUTS  
www.ti.com  
SCAS295S–JANUARY 1993–REVISED MAY 2005  
FEATURES  
•
•
•
Ioff Supports Partial-Power-Down Mode  
Operation  
•
•
•
•
Operate From 1.65 V to 3.6 V  
Inputs Accept Voltages to 5.5 V  
Max tpd of 6.8 ns at 3.3 V  
Latch-Up Performance Exceeds 250 mA Per  
JESD 17  
ESD Protection Exceeds JESD 22  
– 2000-V Human-Body Model (A114-A)  
– 200-V Machine Model (A115-A)  
Typical VOLP (Output Ground Bounce) < 0.8 V  
at VCC = 3.3 V, TA = 25°C  
•
•
Typical VOHV (Output VOH Undershoot) > 2 V at  
VCC = 3.3 V, TA = 25°C  
– 1000-V Charged-Device Model (C101)  
ABC  
Support Mixed-Mode Signal Operation on All  
Ports (5-V Input/Output Voltage With  
3.3-V VCC  
)
SN54LVC373A . . . J OR W PACKAGE  
SN74LVC373A . . . DB, DGV, DW, N,  
NS, OR PW PACKAGE  
SN74LVC373A . . . RGY PACKAGE  
(TOP VIEW)  
SN54LVC373A . . . FK PACKAGE  
(TOP VIEW)  
(TOP VIEW)  
1
20  
1
2
3
4
5
6
7
8
9
10  
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
OE  
1Q  
1D  
V
CC  
3
9
2
1
20 19  
18  
2D  
2Q  
3Q  
3D  
4D  
8D  
7D  
7Q  
6Q  
6D  
2
3
4
5
6
7
8
9
19  
18  
17  
16  
15  
14  
13  
12  
4
5
6
7
8
1Q  
1D  
2D  
2Q  
3Q  
3D  
4D  
4Q  
8Q  
8D  
7D  
7Q  
6Q  
6D  
5D  
5Q  
8Q  
8D  
7D  
7Q  
6Q  
6D  
5D  
5Q  
LE  
17  
16  
15  
14  
2D  
2Q  
3Q  
10 11 12 13  
3D  
4D  
4Q  
GND  
10  
11  
DESCRIPTION/ORDERING INFORMATION  
The SN54LVC373A octal transparent D-type latch is designed for 2.7-V to 3.6-V VCC operation, and the  
SN74LVC373A octal transparent D-type latch is designed for 1.65-V to 3.6-V VCC operation.  
While the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q  
outputs are latched at the logic levels set up at the D inputs.  
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or  
low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the  
bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines  
without interface or pullup components.  
OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered  
while the outputs are in the high-impedance state.  
These devices are fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the  
outputs, preventing damaging current backflow through the devices when they are powered down.  
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup  
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.  
Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators  
in a mixed 3.3-V/5-V system environment.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
PRODUCTION DATA information is current as of publication date.  
Copyright © 1993–2005, Texas Instruments Incorporated  
Products conform to specifications per the terms of the Texas  
On products compliant to MIL-PRF-38535, all parameters are  
Instruments standard warranty. Production processing does not  
tested unless otherwise noted. On all other products, production  
necessarily include testing of all parameters.  
processing does not necessarily include testing of all parameters.  
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SN74LVC373ANSR 替代型号

型号 品牌 替代类型 描述 数据表
SN74LVC373ANSRE4 TI

完全替代

 OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS
74LCX373SJX FAIRCHILD

功能相似

 Low Voltage Octal Transparent Latch with 5V Tolerant Inputs and Outputs

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