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SN74LVC373A-EP PDF预览

SN74LVC373A-EP

更新时间: 2024-10-01 12:47:03
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描述
OCTAL TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS

SN74LVC373A-EP 数据手册

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SN74LVC373A-EP  
OCTAL TRANSPARENT D-TYPE LATCH  
WITH 3-STATE OUTPUTS  
www.ti.com  
SCAS737CNOVEMBER 2003REVISED MARCH 2007  
FEATURES  
Controlled Baseline  
Typical VOLP (Output Ground Bounce)  
<0.8 V at VCC = 3.3 V, TA = 25°C  
One Assembly/Test Site, One Fabrication  
Site  
Typical VOHV (Output VOH Undershoot)  
>2 V at VCC = 3.3 V, TA = 25°C  
Extended Temperature Performance of –40°C  
to 125°C and –55°C to 125°C  
Supports Mixed-Mode Signal Operation on All  
Ports (5-V Input/Output Voltage With 3.3-V  
Enhanced Diminishing Manufacturing Sources  
(DMS) Support  
VCC  
)
Ioff Supports Partial-Power-Down Mode  
Operation  
Enhanced Product-Change Notification  
(1)  
Qualification Pedigree  
ESD Protection Exceeds 2000 V Per  
MIL-STD-883, Method 3015; Exceeds 200 V  
Using Machine Model (C = 200 pF, R = 0)  
DB, DW OR PW PACKAGE  
(TOP VIEW)  
OE  
1Q  
1D  
V
CC  
1
2
3
4
5
6
7
8
9
10  
20  
19  
18  
17  
16  
Operates From 2 V to 3.6 V  
Inputs Accept Voltages to 5.5 V  
Max tpd of 7.5 ns at 3.3 V  
8Q  
8D  
7D  
7Q  
2D  
2Q  
(1) Component qualification in accordance with JEDEC and  
industry standards to ensure reliable operation over an  
extended temperature range. This includes, but is not limited  
to, Highly Accelerated Stress Test (HAST) or biased 85/85,  
temperature cycle, autoclave or unbiased HAST,  
3Q  
15 6Q  
14  
13  
12  
11  
3D  
4D  
6D  
5D  
5Q  
LE  
electromigration, bond intermetallic life, and mold compound  
life. Such qualification testing should not be viewed as  
justifying use of this component beyond specified  
performance and environmental limits.  
4Q  
GND  
DESCRIPTION/ORDERING INFORMATION  
The SN74LVC373A octal transparent D-type latch is designed for 2.7-V to 3.6-V VCC operation.  
While the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q  
outputs are latched at the logic levels set up at the D inputs.  
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or  
low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the  
bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines  
without interface or pullup components.  
OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered  
while the outputs are in the high-impedance state.  
The SN74LVC373A is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the  
outputs, preventing damaging current backflow through the device when it is powered down.  
ORDERING INFORMATION(1)  
TA  
–40°C to 125°C  
–55°C to 125°C  
PACKAGE(2)  
ORDERABLE PART NUMBER  
SN74LVC373AQDWREP  
SN74LVC373AQPWREP  
SN74LVC373AMDBREP  
TOP-SIDE MARKING  
C373AEP  
SOIC – DW  
TSSOP – PW  
SSOP – DB  
Reel of 2000  
Reel of 2000  
Reel of 2000  
C373AEP  
C373AEP  
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI  
website at www.ti.com.  
(2) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at  
www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
PRODUCTION DATA information is current as of publication date.  
Copyright © 2003–2007, Texas Instruments Incorporated  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  

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