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SN74LVC2T45DCTT PDF预览

SN74LVC2T45DCTT

更新时间: 2024-11-04 23:06:23
品牌 Logo 应用领域
德州仪器 - TI 总线收发器输出元件
页数 文件大小 规格书
22页 426K
描述
DUAL BIT DUAL SUPPLY BUS TRANSCEIVER WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS

SN74LVC2T45DCTT 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:SOIC
包装说明:LSSOP, SSOP8,.16针数:8
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01Factory Lead Time:6 weeks
风险等级:1.06其他特性:TWO SEPARATE CONFIGURABLE POWER SUPPLY FOR PORT A AND PORT B
控制类型:COMMON CONTROL计数方向:BIDIRECTIONAL
系列:LVC/LCX/ZJESD-30 代码:R-PDSO-G8
JESD-609代码:e4长度:2.95 mm
逻辑集成电路类型:BUS TRANSCEIVER最大I(ol):0.032 A
湿度敏感等级:1位数:2
功能数量:1端口数量:2
端子数量:8最高工作温度:85 °C
最低工作温度:-40 °C输出特性:3-STATE
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:LSSOP封装等效代码:SSOP8,.16
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, LOW PROFILE, SHRINK PITCH
包装方法:TR峰值回流温度(摄氏度):260
电源:3.3 V最大电源电流(ICC):0.004 mA
Prop。Delay @ Nom-Sup:17.7 ns传播延迟(tpd):17.7 ns
认证状态:Not Qualified座面最大高度:1.3 mm
子类别:Bus Driver/Transceivers最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):1.65 V标称供电电压 (Vsup):1.8 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
翻译:N/A宽度:2.8 mm
Base Number Matches:1

SN74LVC2T45DCTT 数据手册

 浏览型号SN74LVC2T45DCTT的Datasheet PDF文件第2页浏览型号SN74LVC2T45DCTT的Datasheet PDF文件第3页浏览型号SN74LVC2T45DCTT的Datasheet PDF文件第4页浏览型号SN74LVC2T45DCTT的Datasheet PDF文件第5页浏览型号SN74LVC2T45DCTT的Datasheet PDF文件第6页浏览型号SN74LVC2T45DCTT的Datasheet PDF文件第7页 
ꢀꢁ ꢂꢃ ꢄꢅ ꢆꢇ ꢈꢃ ꢉ  
ꢊꢋꢌ ꢄꢍꢎꢏ ꢈ ꢊꢋꢌ ꢄꢍꢀ ꢋꢐꢐꢄꢑ ꢎꢋꢀ ꢈ ꢒꢌꢁꢀ ꢆꢓ ꢏ ꢅꢓ ꢒ  
SCES516E − DECEMBER 2003 − REVISED MAY 2004  
D
D
Available in the Texas Instruments  
NanoStarand NanoFreePackages  
Fully Configurable Dual-Rail Design Allows  
Each Port to Operate Over the Full 1.65-V to  
5.5-V Power-Supply Range  
D
D
I
Supports Partial-Power-Down Mode  
off  
Operation  
Max Data Rates  
− 420 Mbps (3.3-V to 5-V Translation)  
− 210 Mbps (Translate to 3.3 V)  
− 140 Mbps (Translate to 2.5 V)  
− 75 Mbps (Translate to 1.8 V)  
D
V
Isolation Feature − If Either V  
Input  
CC  
CC  
Is at GND, Both Ports Are in the  
High-Impedance State  
D
D
Latch-Up Performance Exceeds 100 mA Per  
JESD 78, Class II  
D
D
D
DIR Input Circuit Referenced to V  
CCA  
ESD Protection Exceeds JESD 22  
− 2000-V Human-Body Model (A114-A)  
− 200-V Machine Model (A115-A)  
Low Power Consumption, 10-µA Max I  
24-mA Output Drive at 3.3 V  
CC  
− 1000-V Charged-Device Model (C101)  
DCT OR DCU PACKAGE  
(TOP VIEW)  
YEP OR YZP PACKAGE  
(BOTTOM VIEW)  
4 5  
3 6  
2 7  
1 8  
GND  
A2  
A1  
DIR  
B2  
B1  
V
V
1
2
3
4
8
7
6
5
V
B1  
B2  
DIR  
CCA  
A1  
A2  
CCB  
V
GND  
CCA  
CCB  
description/ordering information  
This dual-bit noninverting bus transceiver uses two separate configurable power-supply rails. The A port is  
designed to track V . V accepts any supply voltage from 1.65 V to 5.5 V. The B port is designed to track  
CCA CCA  
V
. V  
accepts any supply voltage from 1.65 V to 5.5 V. This allows for universal low-voltage bidirectional  
CCB CCB  
translation between any of the 1.8-V, 2.5-V, 3.3-V, and 5-V voltage nodes.  
The SN74LVC2T45 is designed for asynchronous communication between data buses. The device transmits  
data from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the  
direction-control (DIR) input.  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
T
A
PACKAGE  
NanoStar− WCSP (DSBGA)  
0.23-mm Large Bump − YEP  
SN74LVC2T45YEPR  
SN74LVC2T45YZPR  
Reel of 3000  
_ _ _TB_  
NanoFree− WCSP (DSBGA)  
0.23-mm Large Bump − YZP (Pb-free)  
−40°C to 85°C  
Reel of 3000  
Reel of 250  
Reel of 3000  
SN74LVC2T45DCTR  
SN74LVC2T45DCTT  
SN74LVC2T45DCUR  
SSOP − DCT  
CT2_ _ _  
CT2_  
VSSOP − DCU  
Reel of 250  
SN74LVC2T45DCUT  
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at  
www.ti.com/sc/package.  
DCT: The actual top-side marking has three additional characters that designate the year, month, and assembly/test site.  
DCU: The actual top-side marking has one additional character that designates the assembly/test site.  
YEP/YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one  
following character to designate the assembly/test site. Pin  
1 identifier indicates solder-bump composition  
(1 = SnPb, = Pb-free).  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
NanoStar and NanoFree are trademarks of Texas Instruments.  
ꢈꢥ  
Copyright 2004, Texas Instruments Incorporated  
ꢡ ꢥ ꢢ ꢡꢚ ꢛꢯ ꢝꢜ ꢠ ꢨꢨ ꢦꢠ ꢞ ꢠ ꢟ ꢥ ꢡ ꢥ ꢞ ꢢ ꢪ  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

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