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SN74LVC2G08MDCUREP PDF预览

SN74LVC2G08MDCUREP

更新时间: 2024-11-24 12:47:03
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德州仪器 - TI 输入元件
页数 文件大小 规格书
11页 465K
描述
DUAL 2-INPUT POSITIVE-AND GATE

SN74LVC2G08MDCUREP 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:SOIC
包装说明:VSSOP, TSSOP8,.12,20针数:8
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01Factory Lead Time:6 weeks
风险等级:0.92系列:LVC/LCX/Z
JESD-30 代码:R-PDSO-G8JESD-609代码:e4
长度:2.3 mm负载电容(CL):50 pF
逻辑集成电路类型:AND GATE最大I(ol):0.032 A
湿度敏感等级:1功能数量:2
输入次数:2端子数量:8
最高工作温度:125 °C最低工作温度:-55 °C
封装主体材料:PLASTIC/EPOXY封装代码:VSSOP
封装等效代码:TSSOP8,.12,20封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, VERY THIN PROFILE, SHRINK PITCH包装方法:TR
峰值回流温度(摄氏度):260电源:3.3 V
最大电源电流(ICC):0.01 mAProp。Delay @ Nom-Sup:4.8 ns
传播延迟(tpd):5.7 ns认证状态:Not Qualified
施密特触发器:NO座面最大高度:0.9 mm
子类别:Gates最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):1.65 V标称供电电压 (Vsup):1.8 V
表面贴装:YES技术:CMOS
温度等级:MILITARY端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式:GULL WING端子节距:0.5 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:2 mmBase Number Matches:1

SN74LVC2G08MDCUREP 数据手册

 浏览型号SN74LVC2G08MDCUREP的Datasheet PDF文件第2页浏览型号SN74LVC2G08MDCUREP的Datasheet PDF文件第3页浏览型号SN74LVC2G08MDCUREP的Datasheet PDF文件第4页浏览型号SN74LVC2G08MDCUREP的Datasheet PDF文件第5页浏览型号SN74LVC2G08MDCUREP的Datasheet PDF文件第6页浏览型号SN74LVC2G08MDCUREP的Datasheet PDF文件第7页 
SN74LVC2G08-EP  
DUAL 2-INPUT POSITIVE-AND GATE  
www.ti.com  
SGDS032SEPTEMBER 2007  
1
FEATURES  
Controlled Baseline  
Typical VOHV (Output VOH Undershoot) >2 V at  
VCC = 3.3 V, TA = 25°C  
One Assembly  
Ioff Supports Partial-Power-Down Mode  
Operation  
One Test Site  
One Fabrication Site  
Latch-Up Performance Exceeds 100 mA Per  
JESD 78, Class II  
Enhanced Diminishing Manufacturing Sources  
(DMS) Support  
ESD Protection Exceeds JESD 22  
Enhanced Product-Change Notification  
2000-V Human-Body Model (A114-A)  
1000-V Charged-Device Model (C101)  
(1)  
Qualification Pedigree  
Supports 5-V VCC Operation  
DCU PACKAGE  
(TOP VIEW)  
Inputs Accept Voltages to 5.5 V  
Max tpd of 5.7 ns at 3.3 V  
VCC  
1Y  
2B  
2A  
1
2
3
4
8
7
6
5
1A  
1B  
Low Power Consumption, 10 μA Max ICC  
±24 mA Output Drive at 3.3 V  
2Y  
Typical VOLP (Output Ground Bounce) <0.8 V at  
VCC = 3.3 V, TA = 25°C  
GND  
(1) Component qualification in accordance with JEDEC and  
industry standards to ensure reliable operation over an  
extended temperature range. This includes, but is not limited  
to, Highly Accelerated Stress Test (HAST) or biased 85/85,  
temperature cycle, autoclave or unbiased HAST,  
See mechanical drawings for dimensions.  
electromigration, bond intermetallic life, and mold compound  
life. Such qualification testing should not be viewed as  
justifying use of this component beyond specified  
performance and environmental limits.  
DESCRIPTION/ORDERING INFORMATION  
This dual 2-input positive-AND gate is designed for 1.65-V to 5.5-V VCC operation.  
Y + A B or Y + A ) B  
The SN74LVC2G08 performs the Boolean function  
in positive logic.  
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,  
preventing damaging current backflow through the device when it is powered down.  
ORDERING INFORMATION(1)  
TA  
PACKAGE(2)  
ORDERABLE PART NUMBER  
TOP-SIDE MARKING  
–55°C to 125°C  
VSSOP – DCU  
Reel of 3000  
SN74LVC2G08MDCUREP  
SBNM  
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI  
website at www.ti.com.  
(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.  
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
PRODUCTION DATA information is current as of publication date.  
Copyright © 2007, Texas Instruments Incorporated  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  

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