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SN74LVC1G80DCKT PDF预览

SN74LVC1G80DCKT

更新时间： 2024-11-03 23:11:03
品牌 Logo 应用领域
德州仪器 - TI 触发器锁存器逻辑集成电路光电二极管PC
页数 文件大小 规格书
22页 653K
描述
SINGLE POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP

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中文翻译

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SN74LVC1G80DCKT 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：SOIC
包装说明：SC-70, 5 PIN针数：5
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01Factory Lead Time：6 weeks
风险等级：0.92Samacsys Confidence：3
Samacsys Status：ReleasedSamacsys PartID：268010
Samacsys Pin Count：5Samacsys Part Category：Integrated Circuit
Samacsys Package Category：SOT23 (5-Pin)Samacsys Footprint Name：DCK (R-PDSO-G5)
Samacsys Released Date：2020-05-01 14:46:32Is Samacsys：N
系列：LVC/LCX/ZJESD-30 代码：R-PDSO-G5
JESD-609代码：e4长度：2 mm
负载电容（CL）：50 pF逻辑集成电路类型：D FLIP-FLOP
最大频率@ Nom-Sup：160000000 Hz最大I（ol）：0.032 A
湿度敏感等级：1位数：1
功能数量：1端子数量：5
最高工作温度：125 °C最低工作温度：-40 °C
输出特性：3-STATE输出极性：INVERTED
封装主体材料：PLASTIC/EPOXY封装代码：TSSOP
封装等效代码：TSSOP5/6,.08封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH包装方法：TR
峰值回流温度（摄氏度）：260电源：3.3 V
最大电源电流（ICC）：0.01 mAProp。Delay @ Nom-Sup：12.5 ns
传播延迟（tpd）：9.9 ns认证状态：Not Qualified
座面最大高度：1.1 mm子类别：FF/Latches
最大供电电压 (Vsup)：5.5 V最小供电电压 (Vsup)：1.65 V
标称供电电压 (Vsup)：1.8 V表面贴装：YES
技术：CMOS温度等级：AUTOMOTIVE
端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)端子形式：GULL WING
端子节距：0.65 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED触发器类型：POSITIVE EDGE
宽度：1.25 mm最小 fmax：160 MHz
Base Number Matches：1

SN74LVC1G80DCKT 数据手册

 浏览型号SN74LVC1G80DCKT的Datasheet PDF文件第2页浏览型号SN74LVC1G80DCKT的Datasheet PDF文件第3页浏览型号SN74LVC1G80DCKT的Datasheet PDF文件第4页浏览型号SN74LVC1G80DCKT的Datasheet PDF文件第5页浏览型号SN74LVC1G80DCKT的Datasheet PDF文件第6页浏览型号SN74LVC1G80DCKT的Datasheet PDF文件第7页 
SN74LVC1G80  
SINGLE POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP  
www.ti.com  
SCES221O–APRIL 1999–REVISED JUNE 2005  
FEATURES  
DBV OR DCK PACKAGE  
(TOP VIEW)  
•
Available in the Texas Instruments  
NanoStar™ and NanoFree™ Packages  
1
2
3
D
CLK  
GND  
V
CC  
5
4
•
•
•
•
•
•
Supports 5-V VCC Operation  
Inputs Accept Voltages to 5.5 V  
Max tpd of 4.2 ns at 3.3 V  
Q
Low Power Consumption, 10-µA Max ICC  
±24-mA Output Drive at 3.3 V  
YEA, YEP, YZA, OR YZP PACKAGE  
(BOTTOM VIEW)  
Ioff Supports Partial-Power-Down Mode  
Operation  
3
2
1
4
5
GND  
CLK  
D
Q
•
•
Latch-Up Performance Exceeds 100 mA Per  
JESD 78, Class II  
V
CC  
ESD Protection Exceeds JESD 22  
– 2000-V Human-Body Model (A114-A)  
– 200-V Machine Model (A115-A)  
– 1000-V Charged-Device Model (C101)  
DESCRIPTION/ORDERING INFORMATION  
This single positive-edge-triggered D-type flip-flop is designed for 1.65-V to 5.5-V VCC operation.  
When data at the data (D) input meets the setup time requirement, the data is transferred to the Q output on the  
positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the  
rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting  
the level at the output.  
NanoStar™ and NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the  
die as the package.  
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,  
preventing damaging current backflow through the device when it is powered down.  
ORDERING INFORMATION  
TA  
PACKAGE(1)  
ORDERABLE PART NUMBER TOP-SIDE MARKING(2)  
NanoStar™ – WCSP (DSBGA)  
0.17-mm Small Bump – YEA  
SN74LVC1G80YEAR  
NanoFree™ – WCSP (DSBGA)  
0.17-mm Small Bump – YZA (Pb-free)  
SN74LVC1G80YZAR  
_ _ _CX_  
Reel of 3000  
NanoStar™ – WCSP (DSBGA)  
0.23-mm Large Bump – YEP  
SN74LVC1G80YEPR  
–40°C to 85°C  
NanoFree™ – WCSP (DSBGA)  
0.23-mm Large Bump – YZP (Pb-free)  
SN74LVC1G80YZPR  
Reel of 3000  
Reel of 250  
Reel of 3000  
Reel of 250  
SN74LVC1G80DBVR  
C80_  
SOT (SOT-23) – DBV  
SOT (SC-70) – DCK  
SN74LVC1G80DBVT  
SN74LVC1G80DCKR  
CX_  
SN74LVC1G80DCKT  
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at  
www.ti.com/sc/package.  
(2) DBV/DCK: The actual top-side marking has one additional character that designates the assembly/test site.  
YEA/YZA, YEP/YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one  
following character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, • = Pb-free).  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
NanoStar, NanoFree are trademarks of Texas Instruments.  
PRODUCTION DATA information is current as of publication date.  
Copyright © 1999–2005, Texas Instruments Incorporated  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
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SN74LVC1G80DCKT 替代型号

型号 品牌 替代类型 描述 数据表
SN74LVC1G80DCKRE4 TI

完全替代

 SINGLE POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP
SN74LVC1G80DCKTE4 TI

完全替代

 SINGLE POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP
SN74LVC1G80DCKRG4 TI

完全替代

 SINGLE POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP

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