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SN74LVC1G3157DCK3 PDF预览

SN74LVC1G3157DCK3

更新时间： 2024-11-07 11:08:11
品牌 Logo 应用领域
德州仪器 - TI 开关光电二极管
页数 文件大小 规格书
23页 932K
描述
5V、2:1 (SPDT)、单通道通用模拟开关 | DCK | 6 | -40 to 125

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SN74LVC1G3157DCK3 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Active包装说明：TSSOP,
Reach Compliance Code：compliantFactory Lead Time：1 week
风险等级：5.56模拟集成电路 - 其他类型：SPDT
标称带宽：340 MHzJESD-30 代码：R-PDSO-G6
JESD-609代码：e6长度：2 mm
湿度敏感等级：1信道数量：1
功能数量：1端子数量：6
最高工作温度：125 °C最低工作温度：-40 °C
封装主体材料：PLASTIC/EPOXY封装代码：TSSOP
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
座面最大高度：1.1 mm表面贴装：YES
温度等级：AUTOMOTIVE端子面层：Tin/Bismuth (Sn/Bi)
端子形式：GULL WING端子节距：0.65 mm
端子位置：DUAL宽度：1.25 mm
Base Number Matches：1

SN74LVC1G3157DCK3 数据手册

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SN74LVC1G3157  
SINGLE-POLE, DOUBLE-THROW ANALOG SWITCH  
www.ti.com  
SCES424F–JANUARY 2003–REVISED FEBRUARY 2007  
FEATURES  
•
•
•
Low On-State Resistance, Typically ≈6 Ω  
(VCC = 4.5 V)  
•
1.65-V to 5.5-V VCC Operation  
Latch-Up Performance Exceeds 100 mA Per  
JESD 78, Class II  
•
Useful for Both Analog and Digital  
Applications  
ESD Protection Exceeds JESD 22  
•
•
•
•
Specified Break-Before-Make Switching  
Rail-to-Rail Signal Handling  
–
–
–
2000-V Human-Body Model (A114-A)  
200-V Machine Model (A115-A)  
High Degree of Linearity  
1000-V Charged-Device Model (C101)  
High Speed, Typically 0.5 ns  
(VCC = 3 V, CL = 50 pF)  
DBV PACKAGE  
(TOP VIEW)  
DCK PACKAGE  
(TOP VIEW)  
DRL PACKAGE  
(TOP VIEW)  
1
2
3
6
5
4
B2  
GND  
B1  
S
1
2
3
6
5
4
B2  
GND  
B1  
S
1
2
3
6
5
4
B2  
GND  
B1  
S
VCC  
VCC  
A
VCC  
A
A
DRY PACKAGE  
(TOP VIEW)  
YZP PACKAGE  
(BOTTOM VIEW)  
3
2
1
4
5
6
B1  
GND  
B2  
A
1
2
3
6
5
4
B2  
GND  
B1  
S
VCC  
VCC  
S
A
See mechanical drawings for dimensions.  
DESCRIPTION/ORDERING INFORMATION  
This single-pole, double-throw (SPDT) analog switch is designed for 1.65-V to 5.5-V VCC operation.  
The SN74LVC1G3157 can handle both analog and digital signals. The device permits signals with amplitudes of  
up to VCC (peak) to be transmitted in either direction.  
Applications include signal gating, chopping, modulation or demodulation (modem), and signal multiplexing for  
analog-to-digital and digital-to-analog conversion systems.  
ORDERING INFORMATION  
TA  
PACKAGE(1)  
ORDERABLE PART NUMBER  
TOP-SIDE MARKING(2)  
NanoFree™ – WCSP (DSBGA)  
0.23-mm Large Bump – YZP (Pb-free)  
SON – DRY  
Reel of 3000  
SN74LVC1G3157YZPR  
_ _ _ C5_  
Reel of 5000  
Reel of 3000  
Reel of 3000  
Reel of 4000  
SN74LVC1G3157DRYR  
SN74LVC1G3157DBVR  
SN74LVC1G3157DCKR  
SN74LVC1G3157DRLR  
C5_  
CC5_  
C5_  
C5_  
–40°C to 85°C  
SOT (SOT-23) – DBV  
SOT (SC-70) – DCK  
SOT (SOT-553) – DRL  
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at  
www.ti.com/sc/package.  
(2) DBV/DCK/DRL/DRY: The actual top-side marking has one additional character that designates the assembly/test site.  
YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following  
character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, • = Pb-free).  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
NanoFree is a trademark of Texas Instruments.  
PRODUCTION DATA information is current as of publication date.  
Copyright © 2003–2007, Texas Instruments Incorporated  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
1234567...23

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