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SN74LVC1G132 PDF预览

SN74LVC1G132

更新时间： 2024-11-18 23:11:03
品牌 Logo 应用领域
德州仪器 - TI 触发器输入元件
页数 文件大小 规格书
13页 269K
描述
SINGLE 2-INPUT NAND GATE WITH SCHMITT-TRIGGER INPUTS

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SN74LVC1G132 数据手册

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SCES546A − FEBRUARY 2004 − REVISED AUGUST 2004  
DBV OR DCK PACKAGE  
(TOP VIEW)  
D
Available in Texas Instruments NanoStar  
and NanoFreePackages  
D
D
D
D
D
D
D
D
Supports 5-V V  
Operation  
CC  
1
2
3
5
4
A
B
GND  
V
Y
CC  
Inputs Accept Voltages to 5.5 V  
Max t of 5.3 ns at 3.3 V  
pd  
Low Power Consumption, 10-µA Max I  
CC  
YEP OR YZP PACKAGE  
(BOTTOM VIEW)  
24-mA Output Drive at 3.3 V  
I
Supports Partial-Power-Down Mode  
off  
Operation  
3 4  
2
GND  
B
Y
V
Latch-Up Performance Exceeds 100 mA Per  
JESD 78, Class II  
1 5  
A
CC  
ESD Protection Exceeds JESD 22  
− 2000-V Human-Body Model (A114-A)  
− 200-V Machine Model (A115-A)  
− 1000-V Charged-Device Model (C101)  
description/ordering information  
The SN74LVC1G132 contains one 2-input NAND gate with Schmitt-trigger inputs designed for 1.65-V to 5.5-V  
operation and performs the Boolean function Y = A • B or Y = A + B in positive logic.  
V
CC  
Because of Schmitt action, this device has different input threshold levels for positive-going (V ) and  
T+  
negative-going (V ) signals.  
T−  
This device can be triggered from the slowest of input ramps and still give clean jitter-free output signals.  
This device is fully specified for partial-power-down applications using I . The I circuitry disables the outputs,  
off  
off  
preventing damaging current backflow through the device when it is powered down.  
NanoStarand NanoFreepackage technology is a major breakthrough in IC packaging concepts, using the  
die as the package.  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
†
T
A
PACKAGE  
‡
NanoStar− WCSP (DSBGA)  
0.23-mm Large Bump − YEP  
SN74LVC1G132YEPR  
SN74LVC1G132YZPR  
Reel of 3000  
_ _ _D5_  
NanoFree− WCSP (DSBGA)  
0.23-mm Large Bump − YZP (Pb-free)  
−40°C to 85°C  
Reel of 3000  
Reel of 250  
Reel of 3000  
Reel of 250  
SN74LVC1G132DBVR  
SN74LVC1G132DBVT  
SN74LVC1G132DCKR  
SN74LVC1G132DCKT  
SOT (SOT-23) − DBV  
C3B_  
D5_  
SOT (SC-70) − DCK  
†
‡
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at  
www.ti.com/sc/package.  
DBV/DCK: The actual top-side marking has one additional character that designates the assembly/test site.  
YEP/YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one  
following character to designate the assembly/test site. Pin  
1 identifier indicates solder-bump composition  
(1 = SnPb, • = Pb-free).  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
NanoStar and NanoFree are trademarks of Texas Instruments.  
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Copyright 2004, Texas Instruments Incorporated  
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...13

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