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SN74LVC1G0832DBVT PDF预览

SN74LVC1G0832DBVT

更新时间: 2024-10-01 05:29:35
品牌 Logo 应用领域
德州仪器 - TI 栅极触发器逻辑集成电路光电二极管输入元件
页数 文件大小 规格书
13页 281K
描述
SINGLE 3-INPUT POSITIVE AND-OR GATE

SN74LVC1G0832DBVT 技术参数

是否无铅:不含铅是否Rohs认证:符合
生命周期:Active零件包装代码:SOT-23
包装说明:SOT-23, 6 PIN针数:6
Reach Compliance Code:compliantHTS代码:8542.39.00.01
Factory Lead Time:6 weeks风险等级:1.41
Is Samacsys:N系列:LVC/LCX/Z
JESD-30 代码:R-PDSO-G6JESD-609代码:e4
长度:2.9 mm负载电容(CL):50 pF
逻辑集成电路类型:AND-OR GATE最大I(ol):0.032 A
湿度敏感等级:1功能数量:1
输入次数:3端子数量:6
最高工作温度:125 °C最低工作温度:-40 °C
封装主体材料:PLASTIC/EPOXY封装代码:LSSOP
封装等效代码:TSOP6,.11,37封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, LOW PROFILE, SHRINK PITCH包装方法:TR
峰值回流温度(摄氏度):260电源:3.3 V
最大电源电流(ICC):0.01 mAProp。Delay @ Nom-Sup:5.9 ns
传播延迟(tpd):17.5 ns认证状态:Not Qualified
施密特触发器:NO座面最大高度:1.45 mm
子类别:Gates最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):1.65 V标称供电电压 (Vsup):1.8 V
表面贴装:YES技术:CMOS
温度等级:AUTOMOTIVE端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式:GULL WING端子节距:0.95 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:1.6 mmBase Number Matches:1

SN74LVC1G0832DBVT 数据手册

 浏览型号SN74LVC1G0832DBVT的Datasheet PDF文件第2页浏览型号SN74LVC1G0832DBVT的Datasheet PDF文件第3页浏览型号SN74LVC1G0832DBVT的Datasheet PDF文件第4页浏览型号SN74LVC1G0832DBVT的Datasheet PDF文件第5页浏览型号SN74LVC1G0832DBVT的Datasheet PDF文件第6页浏览型号SN74LVC1G0832DBVT的Datasheet PDF文件第7页 
ꢀꢁꢂ ꢃ ꢄꢅ ꢆꢇ ꢈ ꢉꢊ ꢋꢌ  
ꢀꢍ ꢁꢈ ꢄ ꢎ ꢋ ꢏꢍꢁ ꢐꢑꢒ ꢐꢓ ꢀꢍ ꢒ ꢍꢅꢎ ꢔꢁꢕꢏ ꢓ ꢖ ꢈ ꢔꢒꢎ  
SCES606 − SEPTEMBER 2004  
DBV OR DCK PACKAGE  
(TOP VIEW)  
D
Available in the Texas Instruments  
NanoStarand NanoFreePackages  
D
D
D
D
D
D
Supports 5-V V  
Operation  
CC  
6
5
4
1
2
3
A
GND  
B
C
Inputs Accept Voltages to 5.5 V  
V
Y
CC  
Max t of 5 ns at 3.3 V  
pd  
Low Power Consumption, 10-µA Max I  
CC  
YEP OR YZP PACKAGE  
(BOTTOM VIEW)  
24-mA Output Drive at 3.3 V  
Input Hysteresis Allows Slow Input  
Transition and Better Switching Noise  
Immunity at the Input  
3 4  
2 5  
1 6  
B
GND  
A
Y
V
CC  
(V  
= 250 mV Typ @ 3.3 V)  
hys  
C
D
Can Be Used in Three Combinations:  
− AND-OR Gate  
− AND Gate  
− OR Gate  
D
D
D
I
Supports Partial-Power-Down Mode  
off  
Operation  
Latch-Up Performance Exceeds 100 mA Per  
JESD 78, Class II  
ESD Protection Exceeds JESD 22  
− 2000-V Human-Body Model (A114-A)  
− 200-V Machine Model (A115-A)  
− 1000-V Charged-Device Model (C101)  
description/ordering information  
This device is designed for 1.65-V to 5.5-V V  
operation.  
CC  
The SN74LVC1G0832 is a single 3-input positive AND-OR gate. It performs the Boolean function  
Y + (A B ) ) C in positive logic.  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
T
A
PACKAGE  
NanoStar− WCSP (DSBGA)  
0.23-mm Large Bump − YEP  
SN74LVC1G0832YEPR  
SN74LVC1G0832YZPR  
Reel of 3000  
_ _ _ _  
NanoFree− WCSP (DSBGA)  
0.23-mm Large Bump − YZP (Pb-free)  
−40°C to 85°C  
Reel of 3000  
Reel of 250  
Reel of 3000  
SN74LVC1G0832DBVR  
SN74LVC1G0832DBVT  
SN74LVC1G0832DCKR  
SOT (SOT-23) − DBV  
CDC_  
DC_  
SOT (SC-70) − DCK  
Reel of 250  
SN74LVC1G0832DCKT  
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at  
www.ti.com/sc/package.  
DBV/DCK: The actual top-side marking has one additional character that designates the assembly/test site.  
YEP/YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one  
following character to designate the assembly/test site. Pin  
1 identifier indicates solder-bump composition  
(1 = SnPb, = Pb-free).  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
NanoStar and NanoFree are trademarks of Texas Instruments.  
ꢒꢢ  
Copyright 2004, Texas Instruments Incorporated  
ꢞ ꢢ ꢟ ꢞꢗ ꢘꢬ ꢚꢙ ꢝ ꢥꢥ ꢣꢝ ꢛ ꢝ ꢜ ꢢ ꢞ ꢢ ꢛ ꢟ ꢧ  
ꢟꢗ  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

SN74LVC1G0832DBVT 替代型号

型号 品牌 替代类型 描述 数据表
74LVC1G0832DBVTE4 TI

完全替代

SINGLE 3-INPUT POSITIVE AND-OR GATE
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完全替代

SINGLE 3-INPUT POSITIVE AND-OR GATE
SN74LVC1G0832DBVR TI

完全替代

SINGLE 3-INPUT POSITIVE AND-OR GATE

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