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SN74LVC1G02-EP PDF预览

SN74LVC1G02-EP

更新时间: 2024-11-30 12:47:03
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德州仪器 - TI 输入元件
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14页 545K
描述
SINGLE 2-INPUT POSITIVE-NOR GATE

SN74LVC1G02-EP 数据手册

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SN74LVC1G02-EP  
SINGLE 2-INPUT POSITIVE-NOR GATE  
www.ti.com  
SGLS370AUGUST 2006  
FEATURES  
Supports 5-V VCC Operation  
Controlled Baseline  
Inputs Accept Voltages to 5.5 V  
Max tpd of 3.6 ns at 3.3 V  
– One Assembly  
– One Test Site  
Low Power Consumption, 10-µA Max ICC  
±24-mA Output Drive at 3.3 V  
– One Fabrication Site  
Extended Temperature Performance of –55°C  
to 125°C  
Ioff Supports Partial-Power-Down Mode  
Operation  
Enhanced Diminishing Manufacturing  
Sources (DMS) Support  
Latch-Up Performance Exceeds 100 mA Per  
JESD 78, Class II  
Enhanced Product-Change Notification  
ESD Protection Exceeds JESD 22  
– 2000-V Human-Body Model (A114-A)  
– 200-V Machine Model (A115-A)  
(1)  
Qualification Pedigree  
Available in the Texas Instruments  
NanoStar™ and NanoFree™ Packages  
– 1000-V Charged-Device Model (C101)  
(1) Component qualification in accordance with JEDEC and  
industry standards to ensure reliable operation over an  
extended temperature range. This includes, but is not limited  
to, Highly Accelerated Stress Test (HAST) or biased 85/85,  
temperature cycle, autoclave or unbiased HAST,  
electromigration, bond intermetallic life, and mold compound  
life. Such qualification testing should not be viewed as  
justifying use of this component beyond specified  
performance and environmental limits.  
YEA(A), YEP(A), YZA(A)  
,
DBV(A) PACKAGE  
(TOP VIEW)  
DCK PACKAGE  
DRL(A) PACKAGE  
(TOP VIEW)  
OR YZP(A) PACKAGE  
(BOTTOM VIEW)  
(TOP VIEW)  
3
4
5
GND  
B
Y
1
5
1
2
3
5
A
B
VCC  
A
B
VCC  
1
2
3
5
A
B
VCC  
2
1
2
A
VCC  
4
GND  
Y
4
GND  
3
Y
4
Y
GND  
See mechanical drawings for dimensions.  
A. Product Preview  
DESCRIPTION/ORDERING INFORMATION  
This single 2-input positive-NOR gate is designed for 1.65-V to 5.5-V VCC operation.  
The SN74LVC1G02 performs the Boolean function Y = A + B or Y = A × B in positive logic.  
NanoStar™ and NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the  
die as the package.  
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,  
preventing damaging current backflow through the device when it is powered down.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
NanoStar, NanoFree are trademarks of Texas Instruments.  
PRODUCTION DATA information is current as of publication date.  
Copyright © 2006, Texas Instruments Incorporated  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  

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