5秒后页面跳转
捷配首页

Datasheet > 暂无类别数据> SN74LVC16373DGG
SN74LVC16373DGG PDF预览

SN74LVC16373DGG

更新时间： 2024-10-01 22:13:59
品牌 Logo 应用领域
德州仪器 - TI 锁存器输出元件
页数 文件大小 规格书
6页 99K
描述
16-BIT TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS

阅读下载

中文翻译

获取价格

SN74LVC16373DGG 数据手册

 浏览型号SN74LVC16373DGG的Datasheet PDF文件第2页浏览型号SN74LVC16373DGG的Datasheet PDF文件第3页浏览型号SN74LVC16373DGG的Datasheet PDF文件第4页浏览型号SN74LVC16373DGG的Datasheet PDF文件第5页浏览型号SN74LVC16373DGG的Datasheet PDF文件第6页 
SN74LVC16373  
16-BIT TRANSPARENT D-TYPE LATCH  
WITH 3-STATE OUTPUTS  
SCAS315B – NOVEMBER 1993 – REVISED JULY 1995  
DGG OR DL PACKAGE  
(TOP VIEW)  
Member of the Texas Instruments  
Widebus Family  
EPIC (Enhanced-Performance Implanted  
CMOS) Submicron Process  
1
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
1OE  
1Q1  
1Q2  
GND  
1Q3  
1Q4  
1LE  
1D1  
1D2  
GND  
1D3  
1D4  
2
Typical V  
< 0.8 V at V  
(Output Ground Bounce)  
OLP  
3
= 3.3 V, T = 25°C  
CC  
A
4
Typical V  
> 2 V at V  
(Output V  
Undershoot)  
OHV  
CC  
OH  
5
= 3.3 V, T = 25°C  
A
6
Latch-Up Performance Exceeds 250 mA  
Per JEDEC Standard JESD-17  
7
V
V
CC  
CC  
8
1Q5  
1Q6  
GND  
1Q7  
1Q8  
2Q1  
2Q2  
GND  
2Q3  
2Q4  
1D5  
1D6  
GND  
1D7  
1D8  
2D1  
2D2  
GND  
2D3  
2D4  
9
Bus Hold on Data Inputs Eliminates the  
Need for External Pullup/Pulldown  
Resistors  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
Package Options Include Plastic 300-mil  
Shrink Small-Outline (DL) and Thin Shrink  
Small-Outline (DGG) Packages  
description  
This 16-bit transparent D-type latch is designed  
for 2.7-V to 3.6-V V operation.  
V
V
CC  
CC  
CC  
2Q5  
2Q6  
GND  
2Q7  
2Q8  
2OE  
2D5  
2D6  
GND  
2D7  
2D8  
2LE  
The SN74LVC16373 is particularly suitable for  
implementing buffer registers, I/O ports,  
bidirectional bus drivers, and working registers. It  
can be used as two 8-bit latches or one 16-bit  
latch. Whenthelatch-enable(LE)inputishigh, the  
Q outputs follow the data (D) inputs. When LE is  
taken low, the Q outputs are latched at the levels  
set up at the D inputs.  
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high  
or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive  
the bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus  
lines without need for interface or pullup components.  
OE does not affect internal operations of the latch. Old data can be retained or new data can be entered while  
the outputs are in the high-impedance state.  
To ensure the high-impedance state during power up or power down, OE should be tied to V through a pullup  
CC  
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.  
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.  
The SN74LVC16373 is characterized for operation from –40°C to 85°C.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
EPIC and Widebus are trademarks of Texas Instruments Incorporated.  
Copyright 1995, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
123456

中文翻译

下载PDF

与SN74LVC16373DGG相关器件

型号 品牌 获取价格 描述 数据表
SN74LVC16373DGGR TI

获取价格

 		16-BIT TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS
SN74LVC16373DL TI

获取价格

 		16-BIT TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS
SN74LVC16373DLG4 TI

获取价格

 		16-Bit Transparent D-Type Latch With 3-State Outputs 48-SSOP -40 to 85
SN74LVC16373DLR TI

获取价格

 		具有三态输出的 16 位透明 D 型锁存器 | DL | 48 | -40 to 85
SN74LVC16373DLRG4 TI

获取价格

 		LVC/LCX/Z SERIES, DUAL 8-BIT DRIVER, TRUE OUTPUT, PDSO48, 0.300 INCH, GREEN, PLASTIC, SSOP
SN74LVC16374 TI

获取价格

 		16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS
SN74LVC16374_14 TI

获取价格

 		16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
SN74LVC16374A TI

获取价格

 		16 BIT EDGE TRIGGERED D TYPE FLIP FLOP WITH 3 STATE OUTPUTS
SN74LVC16374A_14 TI

获取价格

 		16-Bit Edge-Triggered D-Type Flip-Flop With 3-State Outputs
SN74LVC16374ADGGR TI

获取价格

 		16 BIT EDGE TRIGGERED D TYPE FLIP FLOP WITH 3 STATE OUTPUTS

与SN74LVC16373DGG相关文章

您还可以找


热门产品
PCB打样/小批量
铝基板
BOM智能配单
PCBA制造
钣金
精密CNC
模具注塑
薄膜开关
精选活动
PCBA打样特惠
四六层板品质升级
铝基板品质升级
一体化电子制造
DFM下载
服务支持
企业认证
产品展示
工厂展示
工艺能力
积分商城
关于捷配
捷配简介
企业文化
公司动态
人才招聘
联系我们
帮助中心
下单流程
付款流程
开票流程
常见问题
全球PCB制造服务专线 400-613-0088

工作时间：9:00-21:00

CEO邮箱：ceo@jiepei.com

投诉邮箱：tousu@jiepei.com

捷配网-微信公众号 微信公众号
捷配网-微信公众号 抖音公众号
资质认证：
合作快递：
支付方式：
Copyright © 2024 Jiepei.com Inc. All Rights Reserved. 版权所有:杭州捷配信息科技有限公司 浙公网安备 33010502006866号 浙ICP备10014259号-119 营业执照ICP证