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SN74LVC126AQPWRQ1 PDF预览

SN74LVC126AQPWRQ1

更新时间： 2024-11-04 12:22:31
品牌 Logo 应用领域
德州仪器 - TI 总线驱动器总线收发器逻辑集成电路光电二极管输出元件
页数 文件大小 规格书
10页 227K
描述
QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS

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SN74LVC126AQPWRQ1 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Obsolete零件包装代码：TSSOP
包装说明：TSSOP, TSSOP14,.25针数：14
Reach Compliance Code：unknownHTS代码：8542.39.00.01
Factory Lead Time：1 week风险等级：7.05
控制类型：ENABLE HIGH系列：LVC/LCX/Z
JESD-30 代码：R-PDSO-G14JESD-609代码：e4
长度：5 mm逻辑集成电路类型：BUS DRIVER
最大I（ol）：0.024 A湿度敏感等级：3
位数：1功能数量：4
端口数量：2端子数量：14
最高工作温度：125 °C最低工作温度：-40 °C
输出特性：3-STATE输出极性：TRUE
封装主体材料：PLASTIC/EPOXY封装代码：TSSOP
封装等效代码：TSSOP14,.25封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH包装方法：TR
峰值回流温度（摄氏度）：260电源：3.3 V
Prop。Delay @ Nom-Sup：5.7 ns传播延迟（tpd）：6.2 ns
认证状态：Not Qualified筛选级别：AEC-Q100
座面最大高度：1.2 mm子类别：Bus Driver/Transceivers
最大供电电压 (Vsup)：3.6 V最小供电电压 (Vsup)：1.65 V
标称供电电压 (Vsup)：2.7 V表面贴装：YES
技术：CMOS温度等级：AUTOMOTIVE
端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)端子形式：GULL WING
端子节距：0.65 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：4.4 mm
Base Number Matches：1

SN74LVC126AQPWRQ1 数据手册

 浏览型号SN74LVC126AQPWRQ1的Datasheet PDF文件第2页浏览型号SN74LVC126AQPWRQ1的Datasheet PDF文件第3页浏览型号SN74LVC126AQPWRQ1的Datasheet PDF文件第4页浏览型号SN74LVC126AQPWRQ1的Datasheet PDF文件第5页浏览型号SN74LVC126AQPWRQ1的Datasheet PDF文件第6页浏览型号SN74LVC126AQPWRQ1的Datasheet PDF文件第7页 
SN74LVC126A-Q1  
www.ti.com .................................................................................................................................................. SCAS763B–FEBRUARY 2004–REVISED APRIL 2008  
QUADRUPLE BUS BUFFER GATE  
WITH 3-STATE OUTPUTS  
1
FEATURES  
•
•
•
•
•
Qualified for Automotive Applications  
Operates From 1.65 V to 3.6 V  
Inputs Accept Voltages to 5.5 V  
Max tpd of 4.7 ns at 3.3 V  
D OR PW PACKAGE  
(TOP VIEW)  
1
2
3
4
5
6
7
14  
13  
12  
11  
10  
9
1OE  
1A  
V
CC  
4OE  
4A  
Typical VOLP (Output Ground Bounce) <0.8 V at  
VCC = 3.3 V, TA = 25°C  
1Y  
2OE  
2A  
4Y  
•
•
•
Typical VOHV (Output VOH Undershoot) >2 V at  
VCC = 3.3 V, TA = 25°C  
3OE  
3A  
2Y  
Latch-Up Performance Exceeds 250 mA Per  
JESD 17  
8
GND  
3Y  
ESD Protection Exceeds JESD 22  
–
–
2000-V Human-Body Model (A114-A)  
200-V Machine Model (A115-A)  
DESCRIPTION/ORDERING INFORMATION  
This quadruple bus buffer gate is designed for 1.65-V to 3.6-V VCC operation.  
The SN74LVC126A features independent line drivers with 3-state outputs. Each output is disabled when the  
associated output-enable (OE) input is low.  
To ensure the high-impedance state during power up or power down, OE should be tied to GND through a  
pulldown resistor; the minimum value of the resistor is determined by the current-sourcing capability of the driver.  
Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of this device as a translator in  
a mixed 3.3-V/5-V system environment.  
ORDERING INFORMATION(1)  
TA  
PACKAGE(2)  
Reel of 2500  
Reel of 2000  
ORDERABLE PART NUMBER  
SN74LVC126AQDRQ1  
TOP-SIDE MARKING  
LC126AQ  
SOIC – D  
–40°C to 125°C  
TSSOP – PW  
SN74LVC126AQPWRQ1  
LC126AQ  
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI  
web site at www.ti.com.  
(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.  
FUNCTION TABLE  
(EACH BUFFER)  
INPUTS  
OE  
OUTPUT  
Y
A
H
L
H
H
L
H
L
X
Z
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
Copyright © 2004–2008, Texas Instruments Incorporated  
1234567...10

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