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SN74LVC126APWTG4 PDF预览

SN74LVC126APWTG4

更新时间： 2024-11-27 11:49:59
品牌 Logo 应用领域
德州仪器 - TI 输出元件
页数 文件大小 规格书
16页 508K
描述
QUADRPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS

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SN74LVC126APWTG4 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Obsolete零件包装代码：TSSOP
包装说明：TSSOP, TSSOP14,.25针数：14
Reach Compliance Code：unknownECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：5.27
控制类型：ENABLE HIGH系列：LVC/LCX/Z
JESD-30 代码：R-PDSO-G14JESD-609代码：e4
长度：5 mm逻辑集成电路类型：BUS DRIVER
最大I（ol）：0.024 A湿度敏感等级：1
位数：1功能数量：4
端口数量：2端子数量：14
最高工作温度：125 °C最低工作温度：-40 °C
输出特性：3-STATE输出极性：TRUE
封装主体材料：PLASTIC/EPOXY封装代码：TSSOP
封装等效代码：TSSOP14,.25封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH包装方法：TUBE
峰值回流温度（摄氏度）：260电源：3.3 V
Prop。Delay @ Nom-Sup：6 ns传播延迟（tpd）：11.3 ns
认证状态：Not Qualified座面最大高度：1.2 mm
子类别：Bus Driver/Transceivers最大供电电压 (Vsup)：3.6 V
最小供电电压 (Vsup)：1.65 V标称供电电压 (Vsup)：1.8 V
表面贴装：YES技术：CMOS
温度等级：AUTOMOTIVE端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：GULL WING端子节距：0.65 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：4.4 mmBase Number Matches：1

SN74LVC126APWTG4 数据手册

 浏览型号SN74LVC126APWTG4的Datasheet PDF文件第2页浏览型号SN74LVC126APWTG4的Datasheet PDF文件第3页浏览型号SN74LVC126APWTG4的Datasheet PDF文件第4页浏览型号SN74LVC126APWTG4的Datasheet PDF文件第5页浏览型号SN74LVC126APWTG4的Datasheet PDF文件第6页浏览型号SN74LVC126APWTG4的Datasheet PDF文件第7页 
SN74LVC126A  
QUADRUPLE BUS BUFFER GATE  
WITH 3-STATE OUTPUTS  
www.ti.com  
SCAS339Q–MARCH 1994–REVISED JULY 2005  
FEATURES  
D, DB, DGV, NS, OR PW PACKAGE  
(TOP VIEW)  
•
Operates From 1.65 V to 3.6 V  
•
Specified From –40°C to 85°C and  
From –40°C to 125°C  
1
2
3
4
5
6
7
14  
13  
12  
11  
10  
9
1OE  
1A  
V
CC  
4OE  
4A  
•
•
•
Inputs Accept Voltages to 5.5 V  
Max tpd of 4.7 ns at 3.3 V  
1Y  
2OE  
2A  
4Y  
Typical VOLP (Output Ground Bounce)  
< 0.8 V at VCC = 3.3 V, TA = 25°C  
3OE  
3A  
2Y  
•
•
•
Typical VOHV (Output VOH Undershoot)  
> 2 V at VCC = 3.3 V, TA = 25°C  
8
GND  
3Y  
Latch-Up Performance Exceeds 250 mA Per  
JESD 17  
RGY PACKAGE  
(TOP VIEW)  
ESD Protection Exceeds JESD 22  
– 2000-V Human-Body Model (A114-A)  
– 200-V Machine Model (A115-A)  
1
14  
1A  
13 4OE  
2
3
4
5
6
12  
11  
10  
9
1Y  
2OE  
2A  
4A  
DESCRIPTION/ORDERING INFORMATION  
4Y  
3OE  
3A  
This quadruple bus buffer gate is designed for 1.65-V  
to 3.6-V VCC operation.  
2Y  
The SN74LVC126A features independent line drivers  
with 3-state outputs. Each output is disabled when  
the associated output-enable (OE) input is low.  
7
8
To ensure the high-impedance state during power up or power down, OE should be tied to GND through a  
pulldown resistor; the minimum value of the resistor is determined by the current-sourcing capability of the driver.  
Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of this device as a translator in  
a mixed 3.3-V/5-V system environment.  
ORDERING INFORMATION  
TA  
PACKAGE(1)  
ORDERABLE PART NUMBER  
SN74LVC126ARGYR  
SN74LVC126AD  
TOP-SIDE MARKING  
–40°C to 85°C  
QFN – RGY  
SOIC – D  
Reel of 1000  
LC126A  
Tube of 50  
Reel of 2500  
Reel of 250  
Reel of 2000  
Reel of 2000  
Tube of 90  
SN74LVC126ADR  
LVC126A  
SN74LVC126ADT  
SOP – NS  
SN74LVC126ANSR  
SN74LVC126ADBR  
SN74LVC126APW  
LVC126A  
LC126A  
–40°C to 125°C  
SSOP – DB  
TSSOP – PW  
TVSOP – DGV  
Reel of 2000  
Reel of 250  
Reel of 2000  
SN74LVC126APWR  
SN74LVC126APWT  
SN74LVC126ADGVR  
LC126A  
LC126A  
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at  
www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
PRODUCTION DATA information is current as of publication date.  
Copyright © 1994–2005, Texas Instruments Incorporated  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
1234567...16

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