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SN74LVC125ADT PDF预览

SN74LVC125ADT

更新时间: 2024-11-20 05:24:51
品牌 Logo 应用领域
德州仪器 - TI 输出元件
页数 文件大小 规格书
12页 282K
描述
QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS

SN74LVC125ADT 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:SOIC
包装说明:SOP, SOP14,.25针数:14
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01Factory Lead Time:1 week
风险等级:1.21控制类型:ENABLE LOW
计数方向:UNIDIRECTIONAL系列:LVC/LCX/Z
JESD-30 代码:R-PDSO-G14JESD-609代码:e4
长度:8.65 mm负载电容(CL):50 pF
逻辑集成电路类型:BUS DRIVER最大I(ol):0.024 A
湿度敏感等级:1位数:1
功能数量:4端口数量:2
端子数量:14最高工作温度:125 °C
最低工作温度:-40 °C输出特性:3-STATE
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP14,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
包装方法:TR峰值回流温度(摄氏度):260
电源:3.3 VProp。Delay @ Nom-Sup:6 ns
传播延迟(tpd):13.8 ns认证状态:Not Qualified
座面最大高度:1.75 mm子类别:Bus Driver/Transceivers
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):1.65 V
标称供电电压 (Vsup):1.8 V表面贴装:YES
技术:CMOS温度等级:AUTOMOTIVE
端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:3.91 mm
Base Number Matches:1

SN74LVC125ADT 数据手册

 浏览型号SN74LVC125ADT的Datasheet PDF文件第2页浏览型号SN74LVC125ADT的Datasheet PDF文件第3页浏览型号SN74LVC125ADT的Datasheet PDF文件第4页浏览型号SN74LVC125ADT的Datasheet PDF文件第5页浏览型号SN74LVC125ADT的Datasheet PDF文件第6页浏览型号SN74LVC125ADT的Datasheet PDF文件第7页 
ꢀꢁ ꢂꢃ ꢄꢅ ꢆꢇ ꢈꢉ ꢊ  
ꢋ ꢌꢊꢍꢎ ꢌꢏꢄ ꢐ ꢑꢌꢀ ꢑꢌꢒ ꢒꢐ ꢎ ꢓ ꢊꢔꢐ  
ꢕ ꢖꢔ ꢗ ꢘ ꢙꢀꢔꢊꢔ ꢐ ꢚ ꢌꢔ ꢏ ꢌꢔꢀ  
SCAS290N − JANUARY 1993 − REVISED FEBRUARY 2004  
D, DB, NS, OR PW PACKAGE  
(TOP VIEW)  
D
D
D
D
D
D
D
D
Operates From 1.65 V to 3.6 V  
Specified From −40°C to 85°C and  
−40°C to 125°C  
Inputs Accept Voltages to 5.5 V  
1
2
3
4
5
6
7
14  
13  
12  
11  
10  
9
1OE  
1A  
1Y  
2OE  
2A  
2Y  
V
CC  
4OE  
Max t of 4.8 ns at 3.3 V  
pd  
4A  
4Y  
3OE  
3A  
3Y  
Typical V  
<0.8 V at V  
(Output Ground Bounce)  
OLP  
CC  
= 3.3 V, T = 25°C  
A
Typical V  
(Output V  
Undershoot)  
OHV  
OH  
8
GND  
>2 V at V  
= 3.3 V, T = 25°C  
CC  
A
Latch-Up Performance Exceeds 250 mA Per  
JESD 17  
RGY PACKAGE  
(TOP VIEW)  
ESD Protection Exceeds JESD 22  
− 2000-V Human-Body Model (A114-A)  
− 200-V Machine Model (A115-A)  
1
14  
− 1000-V Charged-Device Model (C101)  
1A  
13 4OE  
12 4A  
2
3
4
5
6
1Y  
2OE  
2A  
description/ordering information  
11  
10  
9
4Y  
3OE  
3A  
This quadruple bus buffer gate is designed for  
2Y  
1.65-V to 3.6-V V  
operation.  
CC  
7
8
The SN74LVC125A features independent line  
drivers with 3-state outputs. Each output is  
disabled when the associated output-enable (OE)  
input is high.  
To ensure the high-impedance state during power up or power down, OE should be tied to V  
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.  
through a pullup  
CC  
Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of this device as a translator  
in a mixed 3.3-V/5-V system environment.  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
PACKAGE  
T
A
−40°C to 85°C QFN − RGY  
Reel of 1000  
Tube of 50  
SN74LVC125ARGYR  
SN74LVC125AD  
LC125A  
Reel of 2500  
Reel of 250  
Reel of 2000  
Reel of 2000  
Tube of 90  
SN74LVC125ADR  
SN74LVC125ADT  
SN74LVC125ANSR  
SN74LVC125ADBR  
SN74LVC125APW  
SN74LVC125APWR  
SOIC − D  
SOP − NS  
LVC125A  
LVC125A  
LC125A  
−40°C to 125°C  
SSOP − DB  
Reel of 2000  
TSSOP − PW  
LC125A  
Reel of 250  
SN74LVC125APWT  
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design  
guidelines are available at www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
ꢔꢦ  
Copyright 2004, Texas Instruments Incorporated  
ꢢ ꢦ ꢣ ꢢꢛ ꢜꢰ ꢞꢝ ꢡ ꢩꢩ ꢧꢡ ꢟ ꢡ ꢠ ꢦ ꢢ ꢦ ꢟ ꢣ ꢫ  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

SN74LVC125ADT 替代型号

型号 品牌 替代类型 描述 数据表
SN74LVC125ADG4 TI

完全替代

QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS
SN74LVC125ADR TI

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SN74LVC125AD TI

完全替代

QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS

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