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SN74LVC125ADG4 PDF预览

SN74LVC125ADG4

更新时间： 2024-11-04 11:55:59
品牌 Logo 应用领域
德州仪器 - TI 输出元件
页数 文件大小 规格书
17页 613K
描述
QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS

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SN74LVC125ADG4 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：SOIC
包装说明：SOP, SOP14,.25针数：14
Reach Compliance Code：compliantHTS代码：8542.39.00.01
风险等级：0.68控制类型：ENABLE LOW
计数方向：UNIDIRECTIONAL系列：LVC/LCX/Z
JESD-30 代码：R-PDSO-G14JESD-609代码：e4
长度：8.65 mm负载电容（CL）：50 pF
逻辑集成电路类型：BUS DRIVER最大I（ol）：0.024 A
湿度敏感等级：1位数：1
功能数量：4端口数量：2
端子数量：14最高工作温度：125 °C
最低工作温度：-40 °C输出特性：3-STATE
输出极性：TRUE封装主体材料：PLASTIC/EPOXY
封装代码：SOP封装等效代码：SOP14,.25
封装形状：RECTANGULAR封装形式：SMALL OUTLINE
包装方法：TUBE峰值回流温度（摄氏度）：260
电源：3.3 VProp。Delay @ Nom-Sup：6 ns
传播延迟（tpd）：13.8 ns认证状态：Not Qualified
座面最大高度：1.75 mm子类别：Bus Driver/Transceivers
最大供电电压 (Vsup)：3.6 V最小供电电压 (Vsup)：1.65 V
标称供电电压 (Vsup)：1.8 V表面贴装：YES
技术：CMOS温度等级：AUTOMOTIVE
端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)端子形式：GULL WING
端子节距：1.27 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：3.91 mm
Base Number Matches：1

SN74LVC125ADG4 数据手册

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SN74LVC125A  
QUADRUPLE BUS BUFFER GATE  
WITH 3-STATE OUTPUTS  
www.ti.com  
SCAS290O–JANUARY 1993–REVISED AUGUST 2005  
FEATURES  
D, DB, NS, OR PW PACKAGE  
(TOP VIEW)  
•
Operates From 1.65 V to 3.6 V  
•
Specified From –40°C to 85°C  
and –40°C to 125°C  
1
2
3
4
5
6
7
14  
13  
12  
11  
10  
9
1OE  
1A  
V
CC  
4OE  
4A  
4Y  
3OE  
3A  
3Y  
•
•
•
Inputs Accept Voltages to 5.5 V  
Max tpd of 4.8 ns at 3.3 V  
1Y  
2OE  
2A  
2Y  
GND  
Typical VOLP (Output Ground Bounce)  
<0.8 V at VCC = 3.3 V, TA = 25°C  
•
•
•
Typical VOHV (Output VOH Undershoot)  
>2 V at VCC = 3.3 V, TA = 25°C  
8
RGY PACKAGE  
(TOP VIEW)  
Latch-Up Performance Exceeds 250 mA Per  
JESD 17  
ESD Protection Exceeds JESD 22  
– 2000-V Human-Body Model (A114-A)  
– 200-V Machine Model (A115-A)  
1
14  
1A  
13 4OE  
2
3
4
5
6
– 1000-V Charged-Device Model (C101)  
12  
11  
10  
9
1Y  
2OE  
2A  
4A  
4Y  
3OE  
3A  
2Y  
7
8
DESCRIPTION/ORDERING INFORMATION  
This quadruple bus buffer gate is designed for 1.65-V to 3.6-V VCC operation.  
The SN74LVC125A features independent line drivers with 3-state outputs. Each output is disabled when the  
associated output-enable (OE) input is high.  
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup  
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.  
Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of this device as a translator in  
a mixed 3.3-V/5-V system environment.  
ORDERING INFORMATION  
TA  
PACKAGE(1)  
ORDERABLE PART NUMBER  
SN74LVC125ARGYR  
SN74LVC125AD  
TOP-SIDE MARKING  
LC125A  
–40°C to 85°C  
QFN – RGY  
SOIC – D  
Reel of 1000  
Tube of 50  
Reel of 2500  
Reel of 250  
Reel of 2000  
Reel of 2000  
Tube of 90  
SN74LVC125ADR  
LVC125A  
SN74LVC125ADT  
SOP – NS  
SN74LVC125ANSR  
SN74LVC125ADBR  
SN74LVC125APW  
LVC125A  
LC125A  
–40°C to 125°C  
SSOP – DB  
TSSOP – PW  
Reel of 2000  
Reel of 250  
SN74LVC125APWR  
SN74LVC125APWT  
LC125A  
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at  
www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
PRODUCTION DATA information is current as of publication date.  
Copyright © 1993–2005, Texas Instruments Incorporated  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
1234567...17

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SN74LVC125ADG4 替代型号

型号 品牌 替代类型 描述 数据表
SN74LVC125ADT TI

完全替代

 QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS
SN74LVC125ADR TI

完全替代

 QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS
SN74LVC125AD TI

完全替代

 QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS

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