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SN74LVC112ANSR PDF预览

SN74LVC112ANSR

更新时间： 2024-11-03 23:06:23
品牌 Logo 应用领域
德州仪器 - TI 触发器
页数 文件大小 规格书
13页 289K
描述
DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP WITH CLEAR AND PRESET

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SN74LVC112ANSR 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：SOIC
包装说明：SOP, SOP16,.3针数：16
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01Factory Lead Time：6 weeks
风险等级：1.38系列：LVC/LCX/Z
JESD-30 代码：R-PDSO-G16JESD-609代码：e4
长度：10.3 mm负载电容（CL）：50 pF
逻辑集成电路类型：J-K FLIP-FLOP最大频率@ Nom-Sup：150000000 Hz
最大I（ol）：0.024 A湿度敏感等级：1
位数：2功能数量：2
端子数量：16最高工作温度：125 °C
最低工作温度：-40 °C输出极性：COMPLEMENTARY
封装主体材料：PLASTIC/EPOXY封装代码：SOP
封装等效代码：SOP16,.3封装形状：RECTANGULAR
封装形式：SMALL OUTLINE包装方法：TR
峰值回流温度（摄氏度）：260电源：3.3 V
最大电源电流（ICC）：0.01 mAProp。Delay @ Nom-Sup：4.8 ns
传播延迟（tpd）：7.1 ns认证状态：Not Qualified
施密特触发器：No座面最大高度：2 mm
子类别：FF/Latches最大供电电压 (Vsup)：3.6 V
最小供电电压 (Vsup)：2 V标称供电电压 (Vsup)：1.8 V
表面贴装：YES技术：CMOS
温度等级：AUTOMOTIVE端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：GULL WING端子节距：1.27 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
触发器类型：NEGATIVE EDGE宽度：5.3 mm
最小 fmax：150 MHzBase Number Matches：1

SN74LVC112ANSR 数据手册

 浏览型号SN74LVC112ANSR的Datasheet PDF文件第2页浏览型号SN74LVC112ANSR的Datasheet PDF文件第3页浏览型号SN74LVC112ANSR的Datasheet PDF文件第4页浏览型号SN74LVC112ANSR的Datasheet PDF文件第5页浏览型号SN74LVC112ANSR的Datasheet PDF文件第6页浏览型号SN74LVC112ANSR的Datasheet PDF文件第7页 
SN74LVC112A  
DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP  
WITH CLEAR AND PRESET  
www.ti.com  
SCAS289L–JANUARY 1993–REVISED AUGUST 2005  
FEATURES  
D, DB, DGV, NS, OR PW PACKAGE  
(TOP VIEW)  
•
•
•
•
Operates From 1.65 V to 3.6 V  
Inputs Accept Voltages to 5.5 V  
Max tpd of 4.8 ns at 3.3 V  
1CLK  
1K  
V
CC  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
1CLR  
2CLR  
2CLK  
Typical VOLP (Output Ground Bounce)  
1J  
<0.8 V at VCC = 3.3 V, TA = 25°C  
1PRE  
1Q  
•
•
•
Typical VOHV (Output VOH Undershoot)  
>2 V at VCC = 3.3 V, TA = 25°C  
12 2K  
11  
10  
9
1Q  
2J  
Latch-Up Performance Exceeds 250 mA Per  
JESD 17  
2Q  
2PRE  
2Q  
GND  
ESD Protection Exceeds JESD 22  
– 2000-V Human-Body Model (A114-A)  
– 200-V Machine Model (A115-A)  
– 1000-V Charged-Device Model (C101)  
DESCRIPTION/ORDERING INFORMATION  
This dual negative-edge-triggered J-K flip-flop is designed for 1.65-V to 3.6-V VCC operation.  
A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the  
other inputs. When PRE and CLR are inactive (high), data at the J and K inputs meeting the setup-time  
requirements is transferred to the outputs on the negative-going edge of the clock pulse. Clock triggering occurs  
at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval,  
data at the J and K inputs can be changed without affecting the levels at the outputs. The SN74LVC112A can  
perform as a toggle flip-flop by tying J and K high.  
Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators  
in a mixed 3.3-V/5-V system environment.  
ORDERING INFORMATION  
TA  
PACKAGE(1)  
ORDERABLE PART NUMBER  
TOP-SIDE MARKING  
Tube of 40  
SN74LVC112AD  
SOIC – D  
Reel of 2500 SN74LVC112ADR  
Reel of 250 SN74LVC112ADT  
LVC112A  
SOP – NS  
Reel of 2000 SN74LVC112ANSR  
Reel of 2000 SN74LVC112ADBR  
LVC112A  
LC112A  
–40°C to 85°C  
SSOP – DB  
Tube of 90  
Reel of 2000 SN74LVC112APWR  
Reel of 250 SN74LVC112APWT  
Reel of 2000 SN74LVC112ADGVR  
SN74LVC112APW  
TSSOP – PW  
TVSOP – DGV  
LC112A  
LC112A  
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at  
www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
PRODUCTION DATA information is current as of publication date.  
Copyright © 1993–2005, Texas Instruments Incorporated  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
1234567...13

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SN74LVC112ANSR 替代型号

型号 品牌 替代类型 描述 数据表
SN74LVC112APWT TI

完全替代

 DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP WITH CLEAR AND PRESET
SN74LVC112ADGVR TI

完全替代

 DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP WITH CLEAR AND PRESET
SN74LVC112APWE4 TI

完全替代

 DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP WITH CLEAR AND PRESET

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 		DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP WITH CLEAR AND PRESET
SN74LVC112ANSRG4 TI

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 		LVC/LCX/Z SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO16
SN74LVC112APW TI

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 		DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP WITH CLEAR AND PRESET
SN74LVC112APWE4 TI

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 		DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP WITH CLEAR AND PRESET
SN74LVC112APWG4 TI

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 		LVC/LCX/Z SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO16
SN74LVC112APWLE TI

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 		DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP WITH CLEAR AND PRESET
SN74LVC112APWR TI

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 		DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP WITH CLEAR AND PRESET
SN74LVC112APWRE4 TI

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 		DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP WITH CLEAR AND PRESET
SN74LVC112APWRG4 TI

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 		Dual Negative-Edge-Triggered J-K Flip-Flop With Clear And Preset 16-TSSOP -40 to 125
SN74LVC112APWT TI

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 		DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP WITH CLEAR AND PRESET

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