SN74LVC112A

更新时间： 2024-11-05 23:06:23

品牌	Logo	应用领域
德州仪器 - TI		触发器
页数	文件大小	规格书
13页	289K
描述
DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP WITH CLEAR AND PRESET

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SN74LVC112A 数据手册

SN74LVC112A

DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP

WITH CLEAR AND PRESET

www.ti.com

SCAS289L–JANUARY 1993–REVISED AUGUST 2005

FEATURES

D, DB, DGV, NS, OR PW PACKAGE

(TOP VIEW)

•

Operates From 1.65 V to 3.6 V

Inputs Accept Voltages to 5.5 V

Max t_pdof 4.8 ns at 3.3 V

1CLK

1CLR

2CLR

2CLK

Typical V_OLP(Output Ground Bounce)

<0.8 V at V_CC= 3.3 V, T_A= 25°C

1PRE

•

Typical V_OHV(Output V_OHUndershoot)

>2 V at V_CC= 3.3 V, T_A= 25°C

12 2K

Latch-Up Performance Exceeds 250 mA Per

JESD 17

2PRE

GND

ESD Protection Exceeds JESD 22

– 2000-V Human-Body Model (A114-A)

– 200-V Machine Model (A115-A)

– 1000-V Charged-Device Model (C101)

DESCRIPTION/ORDERING INFORMATION

This dual negative-edge-triggered J-K flip-flop is designed for 1.65-V to 3.6-V V_CCoperation.

A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the

other inputs. When PRE and CLR are inactive (high), data at the J and K inputs meeting the setup-time

requirements is transferred to the outputs on the negative-going edge of the clock pulse. Clock triggering occurs

at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval,

data at the J and K inputs can be changed without affecting the levels at the outputs. The SN74LVC112A can

perform as a toggle flip-flop by tying J and K high.

Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators

in a mixed 3.3-V/5-V system environment.

ORDERING INFORMATION

T_A

PACKAGE⁽¹⁾

ORDERABLE PART NUMBER

TOP-SIDE MARKING

Tube of 40

SN74LVC112AD

SOIC – D

Reel of 2500 SN74LVC112ADR

Reel of 250 SN74LVC112ADT

LVC112A

SOP – NS

Reel of 2000 SN74LVC112ANSR

Reel of 2000 SN74LVC112ADBR

LVC112A

LC112A

–40°C to 85°C

SSOP – DB

Tube of 90

Reel of 2000 SN74LVC112APWR

Reel of 250 SN74LVC112APWT

Reel of 2000 SN74LVC112ADGVR

SN74LVC112APW

TSSOP – PW

TVSOP – DGV

LC112A

(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at

www.ti.com/sc/package.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

12 3 4 5 6 7...13

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与SN74LVC112A相关器件

型号	品牌	获取价格	描述	数据表
SN74LVC112AD	TI	获取价格	DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP WITH CLEAR AND PRESET
SN74LVC112ADB	TI	获取价格	DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP WITH CLEAR AND PRESET
SN74LVC112ADBLE	TI	获取价格	DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP WITH CLEAR AND PRESET
SN74LVC112ADBR	TI	获取价格	DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP WITH CLEAR AND PRESET
SN74LVC112ADBRE4	TI	获取价格	DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP WITH CLEAR AND PRESET
SN74LVC112ADE4	TI	获取价格	DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP WITH CLEAR AND PRESET
SN74LVC112ADG4	TI	获取价格	Dual Negative-Edge-Triggered J-K Flip-Flop With Clear And Preset 16-SOIC -40 to 125
SN74LVC112ADGV	TI	获取价格	DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP WITH CLEAR AND PRESET
SN74LVC112ADGVR	TI	获取价格	DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP WITH CLEAR AND PRESET
SN74LVC112ADGVRE4	TI	获取价格	DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP WITH CLEAR AND PRESET

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