生命周期: | Obsolete | 包装说明: | TSSOP, TSSOP14,.25 |
Reach Compliance Code: | unknown | HTS代码: | 8542.39.00.01 |
风险等级: | 5.25 | 系列: | LVC/LCX/Z |
JESD-30 代码: | R-PDSO-G14 | 长度: | 5 mm |
逻辑集成电路类型: | NAND GATE | 功能数量: | 3 |
输入次数: | 3 | 端子数量: | 14 |
最高工作温度: | 85 °C | 最低工作温度: | -40 °C |
封装主体材料: | PLASTIC/EPOXY | 封装代码: | TSSOP |
封装等效代码: | TSSOP14,.25 | 封装形状: | RECTANGULAR |
封装形式: | SMALL OUTLINE, THIN PROFILE, SHRINK PITCH | 认证状态: | Not Qualified |
座面最大高度: | 1.2 mm | 最大供电电压 (Vsup): | 3.6 V |
最小供电电压 (Vsup): | 2.7 V | 标称供电电压 (Vsup): | 3.3 V |
表面贴装: | YES | 技术: | CMOS |
温度等级: | INDUSTRIAL | 端子形式: | GULL WING |
端子节距: | 0.65 mm | 端子位置: | DUAL |
宽度: | 4.4 mm | Base Number Matches: | 1 |
型号 | 品牌 | 获取价格 | 描述 | 数据表 |
SN74LVC112A | TI |
获取价格 |
DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP WITH CLEAR AND PRESET | |
SN74LVC112AD | TI |
获取价格 |
DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP WITH CLEAR AND PRESET | |
SN74LVC112ADB | TI |
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DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP WITH CLEAR AND PRESET | |
SN74LVC112ADBLE | TI |
获取价格 |
DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP WITH CLEAR AND PRESET | |
SN74LVC112ADBR | TI |
获取价格 |
DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP WITH CLEAR AND PRESET | |
SN74LVC112ADBRE4 | TI |
获取价格 |
DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP WITH CLEAR AND PRESET | |
SN74LVC112ADE4 | TI |
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DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP WITH CLEAR AND PRESET | |
SN74LVC112ADG4 | TI |
获取价格 |
Dual Negative-Edge-Triggered J-K Flip-Flop With Clear And Preset 16-SOIC -40 to 125 | |
SN74LVC112ADGV | TI |
获取价格 |
DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP WITH CLEAR AND PRESET | |
SN74LVC112ADGVR | TI |
获取价格 |
DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP WITH CLEAR AND PRESET |