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SN74LV574ANS PDF预览

SN74LV574ANS

更新时间: 2024-11-14 22:37:03
品牌 Logo 应用领域
德州仪器 - TI 总线驱动器总线收发器触发器逻辑集成电路光电二极管输出元件
页数 文件大小 规格书
17页 516K
描述
OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS

SN74LV574ANS 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:SOIC
包装说明:PLASTIC, SOP-20针数:20
Reach Compliance Code:compliantHTS代码:8542.39.00.01
风险等级:5.23Is Samacsys:N
系列:LV/LV-A/LVX/HJESD-30 代码:R-PDSO-G20
JESD-609代码:e4长度:12.6 mm
负载电容(CL):50 pF逻辑集成电路类型:BUS DRIVER
最大频率@ Nom-Sup:45000000 Hz最大I(ol):0.008 A
湿度敏感等级:1位数:8
功能数量:1端口数量:2
端子数量:20最高工作温度:85 °C
最低工作温度:-40 °C输出特性:3-STATE
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP20,.3
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
峰值回流温度(摄氏度):260电源:3.3 V
Prop。Delay @ Nom-Sup:19 ns传播延迟(tpd):23 ns
认证状态:Not Qualified座面最大高度:2 mm
子类别:FF/Latches最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):2 V标称供电电压 (Vsup):2.5 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
触发器类型:POSITIVE EDGE宽度:5.3 mm
Base Number Matches:1

SN74LV574ANS 数据手册

 浏览型号SN74LV574ANS的Datasheet PDF文件第2页浏览型号SN74LV574ANS的Datasheet PDF文件第3页浏览型号SN74LV574ANS的Datasheet PDF文件第4页浏览型号SN74LV574ANS的Datasheet PDF文件第5页浏览型号SN74LV574ANS的Datasheet PDF文件第6页浏览型号SN74LV574ANS的Datasheet PDF文件第7页 
ꢕ ꢑꢋ ꢖ ꢗ ꢏꢀꢋꢇꢋ ꢌ ꢉ ꢘꢋ ꢓꢘ ꢋꢀ  
SCLS412I − APRIL 1998 − REVISED APRIL 2005  
D
D
D
D
D
2-V to 5.5-V V  
Operation  
D
D
D
I
Supports Partial-Power-Down Mode  
CC  
off  
Operation  
Max t of 10 ns at 5 V  
pd  
Latch-Up Performance Exceeds 250 mA Per  
JESD 17  
Typical V  
<0.8 V at V  
(Output Ground Bounce)  
OLP  
CC  
= 3.3 V, T = 25°C  
A
ESD Protection Exceeds JESD 22  
− 2000-V Human-Body Model (A114-A)  
− 200-V Machine Model (A115-A)  
Typical V  
>2.3 V at V  
(Output V  
Undershoot)  
OHV  
CC  
OH  
= 3.3 V, T = 25°C  
A
Support Mixed-Mode Voltage Operation on  
All Ports  
− 1000-V Charged-Device Model (C101)  
SN54LV574A . . . FK PACKAGE  
SN54LV574A . . . J OR W PACKAGE  
SN74LV574A . . . DB, DGV, DW, NS,  
OR PW PACKAGE  
SN74LV574A . . . RGY PACKAGE  
(TOP VIEW)  
(TOP VIEW)  
(TOP VIEW)  
1
20  
OE  
1D  
2D  
3D  
4D  
5D  
6D  
7D  
8D  
V
CC  
1Q  
1
2
3
4
5
6
7
8
9
10  
20  
19  
3
2 1 20 19  
3D  
4D  
5D  
6D  
7D  
2Q  
3Q  
4Q  
18  
17  
16  
4
5
6
7
8
19  
18  
17  
16  
15  
14  
13  
12  
2
3
4
5
6
7
8
9
1D  
2D  
3D  
4D  
5D  
6D  
7D  
8D  
1Q  
2Q  
3Q  
4Q  
5Q  
6Q  
7Q  
8Q  
18 2Q  
17  
16  
15  
14  
13  
12  
11  
3Q  
4Q  
5Q  
6Q  
7Q  
8Q  
CLK  
15 5Q  
14  
6Q  
9 10 11 12 13  
10  
11  
GND  
description/ordering information  
ORDERING INFORMATION  
ORDERABLE  
TOP-SIDE  
MARKING  
PACKAGE  
T
A
PART NUMBER  
SN74LV574ARGYR  
SN74LV574ADW  
SN74LV574ADWR  
SN74LV574ANSR  
SN74LV574ADBR  
SN74LV574APW  
SN74LV574APWR  
SN74LV574APWT  
SN74LV574ADGVR  
SN74LV574AGQNR  
SNJ54LV574AJ  
QFN − RGY  
SOIC − DW  
Reel of 1000  
Tube of 25  
LV574A  
LV574A  
Reel of 2000  
Reel of 2000  
Reel of 2000  
Tube of 70  
SOP − NS  
74LV574A  
LV574A  
SSOP − DB  
−40°C to 85°C  
Reel of 2000  
Reel of 250  
Reel of 2000  
Reel of 1000  
Tube of 20  
TSSOP − PW  
LV574A  
TVSOP − DGV  
VFBGA − GQN  
CDIP − J  
LV574A  
LV574A  
SNJ54LV574AJ  
SNJ54LV574AW  
SNJ54LV574AFK  
−55°C to 125°C CFP − W  
Tube of 85  
SNJ54LV574AW  
LCCC − FK  
Tube of 55  
SNJ54LV574AFK  
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines  
are available at www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 2005, Texas Instruments Incorporated  
ꢘ ꢁ ꢄꢌꢀꢀ ꢉ ꢋꢖ ꢌꢐꢕ ꢑꢀ ꢌ ꢁ ꢉꢋꢌꢍ ꢙꢚ ꢛꢜ ꢝꢞꢟ ꢠꢡꢢ ꢣꢙ ꢟꢞ ꢣꢙꢤ ꢛꢣꢜ ꢓꢐ ꢉ ꢍ ꢘ ꢊꢋ ꢑꢉ ꢁ  
ꢧꢤ ꢦ ꢤ ꢡ ꢢ ꢙ ꢢ ꢦ ꢜ ꢪ  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

SN74LV574ANS 替代型号

型号 品牌 替代类型 描述 数据表
SN74LV574ANSR TI

完全替代

OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS
MC74LVX574MELG ONSEMI

类似代替

Octal D-Type Flip-Flop with 3-State Outputs
74LVX574SJ FAIRCHILD

类似代替

Low Voltage Octal D-Type Flip-Flop with 3-STATE Outputs

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