5秒后页面跳转
SN74LV373PW PDF预览

SN74LV373PW

更新时间: 2024-01-31 14:48:58
品牌 Logo 应用领域
德州仪器 - TI 驱动光电二极管输出元件逻辑集成电路
页数 文件大小 规格书
7页 133K
描述
OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS

SN74LV373PW 技术参数

生命周期:ObsoleteReach Compliance Code:unknown
风险等级:5.83系列:LV/LV-A/LVX/H
JESD-30 代码:R-PDSO-G20长度:6.5 mm
逻辑集成电路类型:BUS DRIVER位数:8
功能数量:1端口数量:2
端子数量:20最高工作温度:85 °C
最低工作温度:-40 °C输出特性:3-STATE
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装等效代码:TSSOP20,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
传播延迟(tpd):26 ns认证状态:Not Qualified
座面最大高度:1.2 mm最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):2.7 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子形式:GULL WING
端子节距:0.65 mm端子位置:DUAL
宽度:4.4 mm

SN74LV373PW 数据手册

 浏览型号SN74LV373PW的Datasheet PDF文件第2页浏览型号SN74LV373PW的Datasheet PDF文件第3页浏览型号SN74LV373PW的Datasheet PDF文件第4页浏览型号SN74LV373PW的Datasheet PDF文件第5页浏览型号SN74LV373PW的Datasheet PDF文件第6页浏览型号SN74LV373PW的Datasheet PDF文件第7页 
ꢉ ꢊꢋꢌꢄ ꢋ ꢍꢌꢁꢀ ꢎꢌꢍꢏ ꢁꢋ ꢐꢑꢋ ꢒꢎ ꢏ ꢄꢌꢋꢊ ꢓ ꢏ  
SCLS196C − FEBRUARY 1993 − REVISED APRIL 1996  
SN54LV373 . . . J OR W PACKAGE  
SN74LV373 . . . DB, DW, OR PW PACKAGE  
(TOP VIEW)  
D EPIC (Enhanced-Performance Implanted  
CMOS) 2-µ Process  
D Typical V  
(Output Ground Bounce)  
OLP  
< 0.8 V at V , T = 25°C  
CC  
A
OE  
1Q  
1D  
2D  
2Q  
3Q  
3D  
4D  
4Q  
V
CC  
8Q  
8D  
1
2
3
4
5
6
7
8
9
20  
19  
18  
D Typical V  
(Output V  
Undershoot)  
OHV  
OH  
> 2 V at V , T = 25°C  
CC  
A
17 7D  
16 7Q  
15 6Q  
14 6D  
13 5D  
12 5Q  
11 LE  
D ESD Protection Exceeds 2000 V Per  
MIL-STD-883C, Method 3015; Exceeds  
200 V Using Machine Model  
(C = 200 pF, R = 0)  
D Latch-Up Performance Exceeds 250 mA  
Per JEDEC Standard JESD-17  
GND 10  
D
Package Options Include Plastic  
Small-Outline (DW), Shrink Small-Outline  
(DB), Thin Shrink Small-Outline (PW),  
Ceramic Flat (W) Packages, Chip Carriers  
(FK), and (J) 300-mil DIPs  
SN54LV373 . . . FK PACKAGE  
(TOP VIEW)  
description  
3
2
1
20 19  
18  
8D  
7D  
7Q  
2D  
2Q  
3Q  
3D  
4D  
4
5
6
7
8
These octal transparent D-type latches are  
designed for 2.7-V to 5.5-V V operation.  
17  
16  
CC  
15 6Q  
14  
9 10 11 12 13  
While the latch-enable (LE) input is high, the Q  
outputs follow the data (D) inputs. When LE is  
taken low, the Q outputs are latched at the logic  
levels set up at the D inputs.  
6D  
A buffered output-enable (OE) input can be used  
to place the eight outputs in either a normal logic  
state (high or low) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive  
the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus  
lines without need for interface or pullup components.  
OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered  
while the outputs are in the high-impedance state.  
The SN74LV373 is available in TI’s shrink small-outline package (DB), which provides the same I/O pin count  
and functionality of standard small-outline packages in less than half the printed-circuit-board area.  
The SN54LV373 is characterized for operation over the full military temperature range of −55°C to 125°C. The  
SN74LV373 is characterized for operation from −40°C to 85°C.  
FUNCTION TABLE  
(each latch)  
INPUTS  
OUTPUT  
Q
OE  
L
LE  
H
H
L
D
H
L
H
L
L
L
X
X
Q
0
H
X
Z
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
EPIC is a trademark of Texas Instruments Incorporated.  
Copyright 1996, Texas Instruments Incorporated  
ꢖ ꢁ ꢄꢏꢀꢀ ꢉ ꢋꢓ ꢏꢍꢔ ꢕꢀ ꢏ ꢁ ꢉꢋꢏꢐ ꢗꢘ ꢙꢚ ꢛꢜꢝ ꢞꢟꢠ ꢡꢗ ꢝꢜ ꢡꢗꢢ ꢙꢡꢚ ꢎꢍ ꢉ ꢐ ꢖ ꢊꢋ ꢕꢉ ꢁ  
ꢥꢢ ꢤ ꢢ ꢟ ꢠ ꢗ ꢠ ꢤ ꢚ ꢨ  
ꢚꢗ  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443  

与SN74LV373PW相关器件

型号 品牌 获取价格 描述 数据表
SN74LV373PWLE TI

获取价格

OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS
SN74LV373PWR TI

获取价格

LV/LV-A/LVX/H SERIES, 8-BIT DRIVER, TRUE OUTPUT, PDSO20, PLASTIC, TSSOP-20
SN74LV374 TI

获取价格

OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS
SN74LV374A TI

获取价格

OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS
SN74LV374ADB TI

获取价格

OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS
SN74LV374ADBLE TI

获取价格

LV/LV-A/LVX/H SERIES, 8-BIT DRIVER, TRUE OUTPUT, PDSO20, SSOP-20
SN74LV374ADBR TI

获取价格

OCTAL EDGE TRIGGERED D TYPE FLIP FLOPS WITH 3 STATE OUTPUTS
SN74LV374ADBRE4 TI

获取价格

OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS
SN74LV374ADBRG4 TI

获取价格

LV/LV-A/LVX/H SERIES, 8-BIT DRIVER, TRUE OUTPUT, PDSO20, GREEN, PLASTIC, SSOP-20
SN74LV374ADGV TI

获取价格

OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS