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SN74LV367ADBLE PDF预览

SN74LV367ADBLE

更新时间： 2024-10-31 13:13:51
品牌 Logo 应用领域
德州仪器 - TI 驱动器输出元件
页数 文件大小 规格书
8页 129K
描述
LV/LV-A/LVX/H SERIES, 6-BIT DRIVER, TRUE OUTPUT, PDSO16, PLASTIC, SSOP-16

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SN74LV367ADBLE 技术参数

生命周期：Obsolete零件包装代码：SOIC
包装说明：SSOP,针数：16
Reach Compliance Code：unknown风险等级：5.55
其他特性：ONE FUNCTION WITH TWO BITS系列：LV/LV-A/LVX/H
JESD-30 代码：R-PDSO-G16长度：6.2 mm
逻辑集成电路类型：BUS DRIVER位数：6
功能数量：1端口数量：2
端子数量：16最高工作温度：85 °C
最低工作温度：-40 °C输出特性：3-STATE
输出极性：TRUE封装主体材料：PLASTIC/EPOXY
封装代码：SSOP封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, SHRINK PITCH传播延迟（tpd）：16 ns
认证状态：Not Qualified座面最大高度：2 mm
最大供电电压 (Vsup)：5.5 V最小供电电压 (Vsup)：2 V
标称供电电压 (Vsup)：2.5 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子形式：GULL WING端子节距：0.65 mm
端子位置：DUAL宽度：5.3 mm
Base Number Matches：1

SN74LV367ADBLE 数据手册

 浏览型号SN74LV367ADBLE的Datasheet PDF文件第2页浏览型号SN74LV367ADBLE的Datasheet PDF文件第3页浏览型号SN74LV367ADBLE的Datasheet PDF文件第4页浏览型号SN74LV367ADBLE的Datasheet PDF文件第5页浏览型号SN74LV367ADBLE的Datasheet PDF文件第6页浏览型号SN74LV367ADBLE的Datasheet PDF文件第7页 
SN54LV367A, SN74LV367A  
HEX BUFFERS AND LINE DRIVERS  
WITH 3-STATE OUTPUTS  
SCLS398B – APRIL 1998 – REVISED SEPTEMBER 1999  
SN54LV367A . . . J OR W PACKAGE  
SN74LV367A . . . D, DB, DGV, NS, OR PW PACKAGE  
(TOP VIEW)  
EPIC (Enhanced-Performance Implanted  
CMOS) Process  
Typical V  
< 0.8 V at V  
(Output Ground Bounce)  
OLP  
= 3.3 V, T = 25°C  
1OE  
1A1  
1Y1  
1A2  
1Y2  
1A3  
1Y3  
GND  
V
CC  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
CC  
A
2OE  
2A2  
2Y2  
Typical V  
> 2 V at V  
(Output V  
Undershoot)  
OHV  
CC  
OH  
= 3.3 V, T = 25°C  
A
Latch-Up Performance Exceeds 100 mA Per  
JESD 78, Class II  
12 2A1  
11  
10  
9
2Y1  
1A4  
1Y4  
ESD Protection Exceeds JESD-22  
– 2000-V Human-Body Model (A114-A)  
– 200-V Machine Model (A115-A)  
– 1000-V Charged-Device Model (C101)  
SN54LV367A . . . FK PACKAGE  
(TOP VIEW)  
Package Options Include Plastic  
Small-Outline (D, NS), Shrink Small-Outline  
(DB), Thin Very Small-Outline (DGV), and  
Thin Shrink Small-Outline (PW) Packages,  
Ceramic Flat (W) Packages, Chip Carriers  
(FK), and DIPs (J)  
3
2
1
20 19  
18  
2A2  
2Y2  
NC  
1Y1  
1A2  
NC  
4
5
6
7
8
17  
16  
description  
15 2A1  
14  
9 10 11 12 13  
1Y2  
1A3  
The ’LV367A devices are hex buffers and line  
drivers designed for 2-V to 5.5-V V operation.  
2Y1  
CC  
These devices are designed specifically to  
improve both the performance and density of  
3-state memory address drivers, clock drivers,  
and bus-oriented receivers and transmitters.  
NC – No internal connection  
The ’LV367A devices are organized as dual 4-line and 2-line buffers/drivers with active-low output-enable (1OE  
and 2OE) inputs. When OE is low, the device passes noninverted data from the A inputs to the Y outputs. When  
OE is high, the outputs are in the high-impedance state.  
To ensure the high-impedance state during power up or power down, OE should be tied to V through a pullup  
CC  
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.  
The SN54LV367A is characterized for operation over the full military temperature range of –55°C to 125°C. The  
SN74LV367A is characterized for operation from –40°C to 85°C.  
FUNCTION TABLE  
(each buffer/driver)  
INPUTS  
OUTPUT  
Y
OE  
A
H
L
L
L
H
L
H
X
Z
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
EPIC is a trademark of Texas Instruments Incorporated.  
Copyright 1999, Texas Instruments Incorporated  
UNLESS OTHERWISE NOTED this document contains PRODUCTION  
DATA information current as of publication date. Products conform to  
specifications per the terms of Texas Instruments standard warranty.  
Production processing does not necessarily include testing of all  
parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
12345678

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