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SN74LV32DB PDF预览

SN74LV32DB

更新时间: 2024-10-31 13:13:51
品牌 Logo 应用领域
德州仪器 - TI 输入元件
页数 文件大小 规格书
10页 221K
描述
LV/LV-A/LVX/H SERIES, QUAD 2-INPUT OR GATE, PDSO14

SN74LV32DB 技术参数

是否Rohs认证:不符合生命周期:Obsolete
Reach Compliance Code:not_compliantHTS代码:8542.39.00.01
风险等级:5.54Is Samacsys:N
系列:LV/LV-A/LVX/HJESD-30 代码:R-PDSO-G14
长度:6.2 mm负载电容(CL):50 pF
逻辑集成电路类型:OR GATE最大I(ol):0.006 A
功能数量:4输入次数:2
端子数量:14最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:SSOP封装等效代码:SSOP14,.3
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, SHRINK PITCH
峰值回流温度(摄氏度):NOT SPECIFIED电源:3.3 V
Prop。Delay @ Nom-Sup:17 ns认证状态:Not Qualified
施密特触发器:NO座面最大高度:2 mm
子类别:Gates最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):2.7 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子形式:GULL WING
端子节距:0.65 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:5.3 mm
Base Number Matches:1

SN74LV32DB 数据手册

 浏览型号SN74LV32DB的Datasheet PDF文件第2页浏览型号SN74LV32DB的Datasheet PDF文件第3页浏览型号SN74LV32DB的Datasheet PDF文件第4页浏览型号SN74LV32DB的Datasheet PDF文件第5页浏览型号SN74LV32DB的Datasheet PDF文件第6页浏览型号SN74LV32DB的Datasheet PDF文件第7页 
ꢀꢁ ꢂꢃ ꢄꢅꢆ ꢇ ꢈ ꢀ ꢁꢉ ꢃꢄꢅ ꢆꢇ  
ꢊ ꢋꢌꢍꢎ ꢋꢏꢄ ꢐ ꢇ ꢑꢒꢁ ꢏꢋꢓ ꢏꢔ ꢀꢒ ꢓ ꢒꢅꢐ ꢑꢔ ꢎ ꢕ ꢌꢓꢐ ꢀ  
SCLS188C − FEBRUARY 1993 − REVISED APRIL 1996  
SN54LV32 . . . J OR W PACKAGE  
SN74LV32 . . . D, DB, OR PW PACKAGE  
(TOP VIEW)  
D
D
D
D
EPIC (Enhanced-Performance Implanted  
CMOS) 2-µ Process  
Typical V  
(Output Ground Bounce)  
OLP  
< 0.8 V at V , T = 25°C  
CC  
A
1A  
1B  
V
CC  
1
2
3
4
5
6
7
14  
13  
12  
11  
Typical V  
(Output V  
Undershoot)  
4B  
4A  
4Y  
OHV  
OH  
> 2 V at V , T = 25°C  
1Y  
CC  
A
2A  
ESD Protection Exceeds 2000 V Per  
MIL-STD-883C, Method 3015; Exceeds  
200 V Using Machine Model  
(C = 200 pF, R = 0)  
2B  
10 3B  
9
8
2Y  
3A  
3Y  
GND  
D
D
Latch-Up Performance Exceeds 250 mA  
Per JEDEC Standard JESD-17  
SN54LV32 . . . FK PACKAGE  
(TOP VIEW)  
Package Options Include Plastic  
Small-Outline (D), Shrink Small-Outline  
(DB), Thin Shrink Small-Outline (PW),  
Ceramic Flat (W) Packages, Chip Carriers  
(FK), and (J) 300-mil DIPs  
3
2
1
20 19  
18  
4A  
NC  
4Y  
1Y  
NC  
2A  
4
5
6
7
8
17  
16  
description  
15 NC  
14  
9 10 11 12 13  
NC  
2B  
These quadruple 2-input positive-OR gates are  
designed for 2.7-V to 5.5-V V operation.  
3B  
CC  
The ’LV32 perform the Boolean function  
Y = A + B or Y =  
in positive logic.  
B
A
@
NC − No internal connection  
The SN74LV32 is packaged in TI’s shrink  
small-outline package (DB), which provides the  
same I/O pin count and functionality of standard  
small-outline packages in less than half the  
printed-circuit-board area.  
The SN54LV32 is characterized for operation over the full military temperature range of −55°C to 125°C. The  
SN74LV32 is characterized for operation from −40°C to 85°C.  
FUNCTION TABLE  
(each gate)  
INPUTS  
OUTPUT  
Y
A
B
X
H
L
H
X
L
H
H
L
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
EPIC is a trademark of Texas Instruments Incorporated.  
Copyright 1996, Texas Instruments Incorporated  
ꢋ ꢁ ꢄꢐꢀꢀ ꢔ ꢓꢖ ꢐꢎꢗ ꢒꢀ ꢐ ꢁ ꢔꢓꢐꢍ ꢘꢙ ꢚꢛ ꢜꢝꢞ ꢟꢠꢡ ꢢꢘ ꢞꢝ ꢢꢘꢣ ꢚꢢꢛ ꢏꢎ ꢔ ꢍ ꢋ ꢤꢓ ꢒꢔ ꢁ  
ꢧꢣ ꢦ ꢣ ꢠ ꢡ ꢘ ꢡ ꢦ ꢛ ꢪ  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443  

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