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SN74LV32A-EP PDF预览

SN74LV32A-EP

更新时间： 2024-11-18 11:58:23
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德州仪器 - TI 输入元件
页数 文件大小 规格书
12页 519K
描述
QUADRUPLE 2-INPUT POSITIVE-OR GATE

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SN74LV32A-EP 数据手册

 浏览型号SN74LV32A-EP的Datasheet PDF文件第2页浏览型号SN74LV32A-EP的Datasheet PDF文件第3页浏览型号SN74LV32A-EP的Datasheet PDF文件第4页浏览型号SN74LV32A-EP的Datasheet PDF文件第5页浏览型号SN74LV32A-EP的Datasheet PDF文件第6页浏览型号SN74LV32A-EP的Datasheet PDF文件第7页 
SN74LV32A-EP  
QUADRUPLE 2-INPUT POSITIVE-OR GATE  
www.ti.com  
SCLS565B–JANUARY 2004–REVISED JANUARY 2006  
FEATURES  
•
Controlled Baseline  
– One Assembly/Test Site, One Fabrication  
Site  
•
•
Supports Mixed-Mode Voltage Operation on  
All Ports  
Ioff Supports Partial-Power-Down Mode  
Operation  
•
•
Extended Temperature Performance of –55°C  
to 125°C  
Enhanced Diminishing Manufacturing  
Sources (DMS) Support  
PW PACKAGE  
(TOP VIEW)  
1A  
1B  
1Y  
2A  
2B  
1
2
3
4
5
6
7
14  
13  
12  
11  
10  
9
V
CC  
•
•
•
•
•
Enhanced Product-Change Notification  
4B  
4A  
4Y  
3B  
3A  
3Y  
(1)  
Qualification Pedigree  
2-V to 5.5-V VCC Operation  
Max tpd of 7.5 ns at 5 V  
Typical VOLP (Output Ground Bounce)  
2Y  
GND  
<0.8 V at VCC = 3.3 V, TA = 25°C  
8
•
Typical VOHV (Output VOH Undershoot)  
>2.3 V at VCC = 3.3 V, TA = 25°C  
(1) Component qualification in accordance with JEDEC and  
industry standards to ensure reliable operation over an  
extended temperature range. This includes, but is not limited  
to, Highly Accelerated Stress Test (HAST) or biased 85/85,  
temperature cycle, autoclave or unbiased HAST,  
electromigration, bond intermetallic life, and mold compound  
life. Such qualification testing should not be viewed as  
justifying use of this component beyond specified  
performance and environmental limits.  
DESCRIPTION/ORDERING INFORMATION  
This quadruple 2-input positive-OR gate is designed for 2-V to 5.5-V VCC operation  
Y + A ) B or Y + A • B  
The SN74LV32A-EP performs the Boolean function  
in positive logic.  
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,  
preventing damaging current backflow through the device when it is powered down.  
ORDERING INFORMATION  
TA  
–40°C to 105°C  
–55°C to 125°C  
PACKAGE(1)  
Tape and reel  
Tape and reel  
ORDERABLE PART NUMBER  
SN74LV32ATPWREP  
TOP-SIDE MARKING  
LV32AEP  
LV32AEP  
TSSOP – PW  
TSSOP – PW  
SN74LV32AMPWREP  
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at  
www.ti.com/sc/package.  
FUNCTION TABLE  
(EACH GATE)  
INPUTS  
OUTPUT  
Y
A
H
X
L
B
X
H
L
H
H
L
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
PRODUCTION DATA information is current as of publication date.  
Copyright © 2004–2006, Texas Instruments Incorporated  
Products conform to specifications per the terms of the Texas  
On products compliant to MIL-PRF-38535, all parameters are  
Instruments standard warranty. Production processing does not  
tested unless otherwise noted. On all other products, production  
necessarily include testing of all parameters.  
processing does not necessarily include testing of all parameters.  
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