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SN74LV245DBLE PDF预览

SN74LV245DBLE

更新时间: 2024-11-24 12:15:03
品牌 Logo 应用领域
德州仪器 - TI 总线收发器输出元件
页数 文件大小 规格书
7页 125K
描述
OCTAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS

SN74LV245DBLE 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Obsolete零件包装代码:SSOP
包装说明:SSOP, SSOP20,.3针数:20
Reach Compliance Code:not_compliantHTS代码:8542.39.00.01
风险等级:5.48其他特性:WITH DIRECTION CONTROL
控制类型:COMMON CONTROL计数方向:BIDIRECTIONAL
系列:LV/LV-A/LVX/HJESD-30 代码:R-PDSO-G20
长度:7.2 mm负载电容(CL):50 pF
逻辑集成电路类型:BUS TRANSCEIVER最大I(ol):0.016 A
位数:8功能数量:1
端口数量:2端子数量:20
最高工作温度:85 °C最低工作温度:-40 °C
输出特性:3-STATE输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:SSOP
封装等效代码:SSOP20,.3封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, SHRINK PITCH包装方法:TAPE AND REEL
峰值回流温度(摄氏度):NOT SPECIFIED电源:3.3 V
Prop。Delay @ Nom-Sup:14 ns传播延迟(tpd):18 ns
认证状态:Not Qualified座面最大高度:2 mm
子类别:Bus Driver/Transceivers最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):2.7 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子形式:GULL WING
端子节距:0.65 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED翻译:N/A
宽度:5.3 mmBase Number Matches:1

SN74LV245DBLE 数据手册

 浏览型号SN74LV245DBLE的Datasheet PDF文件第2页浏览型号SN74LV245DBLE的Datasheet PDF文件第3页浏览型号SN74LV245DBLE的Datasheet PDF文件第4页浏览型号SN74LV245DBLE的Datasheet PDF文件第5页浏览型号SN74LV245DBLE的Datasheet PDF文件第6页浏览型号SN74LV245DBLE的Datasheet PDF文件第7页 
ꢉ ꢊꢋꢌꢄ ꢍꢎꢀ ꢋ ꢏꢌꢁꢀꢊ ꢐ ꢑꢅ ꢐ ꢏ  
SCLS075E − JANUARY 1991 − REVISED APRIL 1996  
SN54LV245 . . . J OR W PACKAGE  
SN74LV245 . . . DB, DW, OR PW PACKAGE  
(TOP VIEW)  
D EPIC (Enhanced-Performance Implanted  
CMOS) 2-µ Process  
D Typical V  
(Output Ground Bounce)  
OLP  
< 0.8 V at V , T = 25°C  
CC  
A
DIR  
A1  
1
2
3
4
5
6
7
8
9
10  
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
V
CC  
D Typical V  
(Output V  
Undershoot)  
OE  
B1  
B2  
B3  
B4  
B5  
B6  
B7  
B8  
OHV  
CC  
OH  
> 2 V at V , T = 25°C  
A2  
A
A3  
D ESD Protection Exceeds 2000 V Per  
MIL-STD-883C, Method 3015; Exceeds  
200 V Using Machine Model  
A4  
A5  
A6  
(C = 200 pF, R = 0)  
A7  
D Latch-Up Performance Exceeds 250 mA  
A8  
Per JEDEC Standard JESD-17  
GND  
D
Package Options Include Plastic  
Small-Outline (DW), Shrink Small-Outline  
(DB), Thin Shrink Small-Outline (PW),  
Ceramic Flat (W) Packages, Chip Carriers  
(FK), and (J) 300-mil DIPs  
SN54LV245 . . . FK PACKAGE  
(TOP VIEW)  
description  
3
2
1
20 19  
18  
B1  
B2  
B3  
B4  
B5  
A3  
A4  
A5  
A6  
A7  
4
5
6
7
8
These octal bus transceivers are designed for  
2.7-V to 5.5-V V operation.  
17  
16  
15  
14  
CC  
The ’LV245 are designed for asynchronous  
communication between data buses. The device  
transmits data from the A bus to the B bus or from  
the B bus to the A bus, depending upon the logic  
level at the direction-control (DIR) input. The  
output-enable (OE) input can be used to disable  
the device so the buses are effectively isolated.  
9 10 11 12 13  
The SN74LV245 is available in TI’s shrink small-outline package (DB), which provides the same I/O pin count  
and functionality of standard small-outline packages in less than half the printed-circuit-board area.  
The SN54LV245 is characterized for operation over the full military temperature range of −55°C to 125°C. The  
SN74LV245 is characterized for operation from −40°C to 85°C.  
FUNCTION TABLE  
INPUTS  
OPERATION  
OE  
L
DIR  
L
B data to A bus  
A data to B bus  
Isolation  
L
H
H
X
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
EPIC is a trademark of Texas Instruments Incorporated.  
Copyright 1996, Texas Instruments Incorporated  
ꢎ ꢁ ꢄꢐꢀꢀ ꢉ ꢋꢓ ꢐꢏꢒ ꢑꢀ ꢐ ꢁ ꢉꢋꢐꢗ ꢘꢙ ꢚꢛ ꢜꢝꢞ ꢟꢠꢡ ꢢꢘ ꢞꢝ ꢢꢘꢣ ꢚꢢꢛ ꢖꢏ ꢉ ꢗ ꢎ ꢊꢋ ꢑꢉ ꢁ  
ꢦꢣ ꢥ ꢣ ꢠ ꢡ ꢘ ꢡ ꢥ ꢛ ꢩ  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443  

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