ꢀꢁꢂ ꢃ ꢄꢅꢆ ꢇ ꢈꢉ ꢀꢁ ꢊꢃ ꢄꢅ ꢆꢇ ꢈ
ꢋꢌꢈ ꢄ ꢃ ꢍꢎꢁ ꢏꢌꢐ ꢏꢑ ꢀꢎ ꢐ ꢎꢅꢒ ꢍꢁꢈꢁ ꢋ ꢓ ꢈꢐꢒ
SCES339E − SEPTEMBER 2000 − REVISED APRIL 2005
SN54LV20A . . . J OR W PACKAGE
SN74LV20A . . . D, DB, DGV, NS, OR PW PACKAGE
(TOP VIEW)
D
D
D
D
D
D
D
2-V to 5.5-V V
Operation
CC
Max t of 6 ns at 5 V
pd
Typical V
<0.8 V at V
(Output Ground Bounce)
OLP
CC
= 3.3 V, T = 25°C
1A
1B
V
CC
1
2
3
4
5
6
7
14
13
12
11
A
2D
2C
NC
Typical V
>2.3 V at V
(Output V
Undershoot)
OHV
CC
OH
NC
1C
= 3.3 V, T = 25°C
A
I
Supports Partial-Power-Down Mode
off
1D
10 2B
Operation
9
8
1Y
2A
2Y
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
GND
ESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
SN54LV20A . . . FK PACKAGE
(TOP VIEW)
− 1000-V Charged-Device Model (C101)
description/ordering information
3
2
1
20 19
18
2C
NC
NC
NC
NC
1C
NC
1D
4
5
6
7
8
These dual 4-input positive-NAND gates are
17
16
designed for 2-V to 5.5-V V
operation.
CC
15 NC
14
9 10 11 12 13
The ’LV20A devices perform the Boolean function
Y = A • B • C • D or Y = A + B + C + D in positive
logic.
2B
These devices are fully specified for
partial-power-down applications using I . The I
off
off
NC − No internal connection
circuitry disables the outputs, preventing
damaging current backflow through the devices
when they are powered down.
ORDERING INFORMATION
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
†
PACKAGE
T
A
Tube of 50
SN74LV20AD
SOIC − D
LV20A
Reel of 2500
Reel of 2000
Reel of 2000
Tube of 90
SN74LV20ADR
SN74LV20ANSR
SN74LV20ADBR
SN74LV20APW
SN74LV20APWR
SN74LV20APWT
SN74LV20ADGVR
SNJ54LV20AJ
SOP − NS
74LV20A
LV20A
SSOP − DB
−40°C to 85°C
Reel of 2000
Reel of 250
Reel of 2000
Tube of 25
TSSOP − PW
LV20A
TVSOP − DGV
CDIP − J
LV20A
SNJ54LV20AJ
SNJ54LV20AW
SNJ54LV20AFK
−55°C to 125°C CFP − W
Tube of 150
Tube of 55
SNJ54LV20AW
SNJ54LV20AFK
LCCC − FK
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines
are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2005, Texas Instruments Incorporated
ꢌ ꢁ ꢄꢒꢀꢀ ꢑ ꢐꢔ ꢒꢕꢖ ꢎꢀ ꢒ ꢁ ꢑꢐꢒꢋ ꢗꢘ ꢙꢚ ꢛꢜꢝ ꢞꢟꢠ ꢡꢗ ꢝꢜ ꢡꢗꢢ ꢙꢡꢚ ꢏꢕ ꢑ ꢋ ꢌ ꢣꢐ ꢎꢑ ꢁ
ꢗ
ꢋ
ꢈ
ꢐ
ꢈ
ꢙꢡ
ꢤ
ꢜ
ꢥ
ꢟ
ꢢ
ꢗꢙ
ꢜ
ꢡ
ꢝ
ꢞ
ꢥ
ꢥ
ꢠ
ꢡ
ꢗ
ꢢ
ꢚ
ꢜ
ꢤ
ꢦ
ꢞ
ꢧ
ꢨ
ꢙ
ꢝ
ꢢ
ꢗ
ꢙ
ꢜ
ꢡ
ꢛ
ꢢ
ꢠ
ꢩ
ꢏ
ꢥ
ꢜ
ꢛ
ꢞ
ꢝ
ꢗ
ꢚ
ꢝ
ꢜ
ꢡ
ꢤ
ꢜ
ꢥ
ꢟ
ꢗ
ꢜ
ꢚ
ꢦ
ꢠ
ꢝ
ꢙ
ꢤ
ꢙ
ꢝ
ꢢ
ꢗ
ꢙ
ꢜ
ꢡ
ꢚ
ꢦ
ꢠ
ꢥ
ꢗ
ꢘ
ꢠ
ꢗ
ꢠ
ꢥꢟ
ꢚ
ꢜ
ꢤ
ꢐ
ꢠ
ꢪ
ꢢ
ꢚ
ꢎ
ꢡ
ꢚ
ꢗ
ꢥ
ꢞ
ꢟ
ꢠ
ꢡ
ꢗ
ꢚ
ꢚ
ꢗ
ꢢ
ꢡ
ꢛ
ꢢ
ꢥ
ꢛ
ꢫ
ꢢ
ꢥ
ꢥ
ꢢ
ꢡ
ꢗ
ꢬ
ꢩ
ꢏ
ꢥ
ꢜ
ꢛ
ꢞ
ꢝ
ꢗ
ꢙ
ꢜ
ꢡ
ꢦꢢ ꢥ ꢢ ꢟ ꢠ ꢗ ꢠ ꢥ ꢚ ꢩ
ꢦ
ꢥ
ꢜ
ꢝ
ꢠ
ꢚ
ꢚ
ꢙ
ꢡ
ꢭ
ꢛ
ꢜ
ꢠ
ꢚ
ꢡ
ꢜ
ꢗ
ꢡ
ꢠ
ꢝ
ꢠ
ꢚ
ꢚ
ꢢ
ꢥ
ꢙ
ꢨ
ꢬ
ꢙ
ꢡ
ꢝ
ꢨ
ꢞ
ꢛ
ꢠ
ꢗ
ꢠ
ꢚ
ꢗ
ꢙ
ꢡ
ꢭ
ꢜ
ꢤ
ꢢ
ꢨ
ꢨ
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265