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SN74LV161284 PDF预览

SN74LV161284

更新时间： 2024-11-24 22:36:51
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德州仪器 - TI /
页数 文件大小 规格书
11页 185K
描述
19-BIT BUS INTERFACE

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SN74LV161284 数据手册

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SN74LV161284  
19-BIT BUS INTERFACE  
SCLS426C – OCTOBER 1998 – REVISED NOVEMBER 2002  
DGG OR DL PACKAGE  
(TOP VIEW)  
4.5-V to 5.5-V V  
Operation  
CC  
1.4-kΩ Pullup Resistors Integrated on All  
Open-Drain Outputs Eliminate the Need for  
Discrete Resistors  
HD  
A9  
1
48 DIR  
47 Y9  
2
Designed for IEEE Std 1284-I (Level-1 Type)  
and IEEE Std 1284-II (Level-2 Type)  
Electrical Specifications  
A10  
A11  
A12  
A13  
3
46 Y10  
45 Y11  
4
5
44  
Y12  
Flow-Through Architecture Optimizes PCB  
Layout  
6
43 Y13  
7
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
V
V
CABLE  
CC  
CC  
A1  
Latch-Up Performance Exceeds 250 mA Per  
JEDEC 17  
8
B1  
B2  
GND  
B3  
B4  
B5  
B6  
GND  
B7  
B8  
9
A2  
GND  
A3  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
ESD Protection Exceeds JESD 22  
– 4000-V Human-Body Model (A114-A)  
– 300-V Machine Model (A115-A)  
A4  
A5  
A6  
– 2000-V Charged-Device Model (C101)  
description/ordering information  
GND  
A7  
The SN74LV161284 is designed for 4.5-V to  
A8  
5.5-V V  
operation. This device provides  
CC  
V
V
CABLE  
CC  
CC  
asynchronous two-way communication between  
data buses. The control-function implementation  
minimizes external timing requirements.  
PERI LOGIC IN  
PERI LOGIC OUT  
C14  
C15  
C16  
A14  
A15  
A16  
A17  
This device has eight bidirectional bits; data can  
flow in the A-to-B direction when DIR is high, and  
in the B-to-A direction when DIR is low. This  
device also has five drivers, which drive the cable  
side, and four receivers. The SN74LV161284 has  
one receiver dedicated to the HOST LOGIC line  
and a driver to drive the PERI LOGIC line.  
C17  
HOST LOGIC OUT  
HOST LOGIC IN  
The output drive mode is determined by the high-drive (HD) control pin. When HD is high, the B, Y, and  
PERI LOGIC OUT outputs are in a totem-pole configuration, and in an open-drain configuration when HD is low.  
This meets the drive requirements as specified in the IEEE Std 1284-I (level-1 type) and IEEE Std 1284-II  
(level-2 type) parallel peripheral-interface specifications. Except for HOST LOGIC IN and PERI LOGIC OUT,  
all cable-side pins have a 1.4-kΩ integrated pullup resistor. The pullup resistor is switched off if the associated  
output driver is in the low state or if the output voltage is above V  
PERI LOGIC OUT is set to low.  
CABLE. If V  
CABLE is off,  
CC  
CC  
The device has two supply voltages. V  
output buffers of the cable side only and is designed for 4.5-V to 5.5-V operation.  
is designed for 4.5-V to 5.5-V operation. V  
CABLE supplies the  
CC  
CC  
ORDERING INFORMATION  
ORDERABLE  
TOP-SIDE  
MARKING  
†
PACKAGE  
T
A
PART NUMBER  
SN74LV161284DL  
SN74LV161284DLR  
SN74LV161284DGGR  
Tube  
SSOP – DL  
TSSOP – DGG  
LV161284  
LV161284  
–40°C to 85°C  
Tape and reel  
Tape and reel  
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are  
available at www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 2002, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...11

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