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SN74LV125ATPWTE4 PDF预览

SN74LV125ATPWTE4

更新时间： 2024-11-28 11:58:23
品牌 Logo 应用领域
德州仪器 - TI 总线驱动器总线收发器逻辑集成电路光电二极管输出元件
页数 文件大小 规格书
19页 861K
描述
QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS

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SN74LV125ATPWTE4 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Obsolete零件包装代码：TSSOP
包装说明：GREEN, PLASTIC, TSSOP-14针数：14
Reach Compliance Code：unknownHTS代码：8542.39.00.01
风险等级：5.51Is Samacsys：N
控制类型：ENABLE LOW系列：LV/LV-A/LVX/H
JESD-30 代码：R-PDSO-G14JESD-609代码：e4
长度：5 mm负载电容（CL）：50 pF
逻辑集成电路类型：BUS DRIVER最大I（ol）：0.016 A
湿度敏感等级：1位数：4
功能数量：1端口数量：2
端子数量：14最高工作温度：125 °C
最低工作温度：-40 °C输出特性：3-STATE
输出极性：TRUE封装主体材料：PLASTIC/EPOXY
封装代码：TSSOP封装等效代码：TSSOP14,.25
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
包装方法：TR峰值回流温度（摄氏度）：260
电源：5 VProp。Delay @ Nom-Sup：10.5 ns
传播延迟（tpd）：8.5 ns认证状态：Not Qualified
座面最大高度：1.2 mm子类别：Bus Driver/Transceivers
最大供电电压 (Vsup)：5.5 V最小供电电压 (Vsup)：4.5 V
标称供电电压 (Vsup)：5 V表面贴装：YES
技术：CMOS温度等级：AUTOMOTIVE
端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)端子形式：GULL WING
端子节距：0.65 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：4.4 mm
Base Number Matches：1

SN74LV125ATPWTE4 数据手册

 浏览型号SN74LV125ATPWTE4的Datasheet PDF文件第2页浏览型号SN74LV125ATPWTE4的Datasheet PDF文件第3页浏览型号SN74LV125ATPWTE4的Datasheet PDF文件第4页浏览型号SN74LV125ATPWTE4的Datasheet PDF文件第5页浏览型号SN74LV125ATPWTE4的Datasheet PDF文件第6页浏览型号SN74LV125ATPWTE4的Datasheet PDF文件第7页 
SN74LV125AT  
QUADRUPLE BUS BUFFER GATE  
WITH 3-STATE OUTPUTS  
www.ti.com  
SCES629A–MAY 2005–REVISED AUGUST 2005  
FEATURES  
•
•
•
•
Inputs Are TTL-Voltage Compatible  
4.5-V to 5.5-V VCC Operation  
Typical tpd of 3.8 ns at 5 V  
•
•
•
Ioff Supports Partial-Power-Down Mode  
Operation  
Latch-Up Performance Exceeds 250 mA Per  
JESD 17  
Typical VOLP (Output Ground Bounce)  
<0.8 V at VCC = 5 V, TA = 25°C  
ESD Protection Exceeds JESD 22  
– 2000-V Human-Body Model (A114-A)  
– 200-V Machine Model (A115-A)  
•
•
Typical VOHV (Output VOH Undershoot)  
>2.3 V at VCC = 5 V, TA = 25°C  
Support Mixed-Mode Voltage Operation on All  
Ports  
– 1000-V Charged-Device Model (C101)  
XXXX  
XXXX  
RGY PACKAGE  
(TOP VIEW)  
D, DB, NS, OR PW PACKAGE  
(TOP VIEW)  
1OE  
1A  
V
CC  
1
2
3
4
5
6
7
14  
13  
12  
11  
1
14  
4OE  
4A  
1A  
1Y  
13 4OE  
1Y  
2
3
4
5
6
12  
11  
10  
9
4A  
2OE  
2A  
4Y  
2OE  
2A  
4Y  
3OE  
3A  
10 3OE  
9
8
2Y  
3A  
3Y  
2Y  
GND  
7
8
DESCRIPTION/ORDERING INFORMATION  
The SN74LV125AT is a quadruple bus buffer gate. This device features independent line drivers with 3-state  
outputs. Each output is disabled when the associated output-enable (OE) input is high.  
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup  
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.  
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,  
preventing damaging current backflow through the device when it is powered down.  
ORDERING INFORMATION  
TA  
PACKAGE(1)  
ORDERABLE PART NUMBER  
SN74LV125ATRGYR  
SN74LV125ATD  
TOP-SIDE MARKING  
VV125  
QFN – RGY  
SOIC – D  
Reel of 1000  
Tube of 50  
Reel of 2500  
Tube of 50  
Reel of 2000  
Tube of 80  
Reel of 2000  
Tube of 90  
Reel of 2000  
Reel of 250  
SN74LV125ATDR  
SN74LV125ATNS  
SOP – NS  
SN74LV125ATNSR  
SN74LV125ATDB  
–40°C to 85°C  
LV125AT  
SSOP – DB  
SN74LV125ATDBR  
SN74LV125ATPW  
SN74LV125ATPWR  
SN74LV125ATPWT  
TSSOP – PW  
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at  
www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
PRODUCTION DATA information is current as of publication date.  
Copyright © 2005, Texas Instruments Incorporated  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
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