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SN74LV02APWR PDF预览

SN74LV02APWR

更新时间: 2024-11-19 23:03:15
品牌 Logo 应用领域
德州仪器 - TI 输入元件
页数 文件大小 规格书
14页 409K
描述
QUADRUPLE 2-INPUT POSITIVE-NOR GATES

SN74LV02APWR 数据手册

 浏览型号SN74LV02APWR的Datasheet PDF文件第2页浏览型号SN74LV02APWR的Datasheet PDF文件第3页浏览型号SN74LV02APWR的Datasheet PDF文件第4页浏览型号SN74LV02APWR的Datasheet PDF文件第5页浏览型号SN74LV02APWR的Datasheet PDF文件第6页浏览型号SN74LV02APWR的Datasheet PDF文件第7页 
ꢀꢁꢂ ꢃ ꢄꢅꢆ ꢇ ꢈꢉ ꢀꢁ ꢊꢃ ꢄꢅ ꢆꢇ ꢈ  
SCLS390J − APRIL 1998 − REVISED APRIL 2005  
D
D
D
D
D
2-V to 5.5-V V  
Operation  
D
D
D
I
Supports Partial-Power-Down Mode  
CC  
off  
Operation  
Max t of 6.5 ns at 5 V  
pd  
Latch-Up Performance Exceeds 250 mA Per  
JESD 17  
Typical V  
<0.8 V at V  
(Output Ground Bounce)  
OLP  
CC  
= 3.3 V, T = 25°C  
A
ESD Protection Exceeds JESD 22  
− 2000-V Human-Body Model (A114-A)  
− 200-V Machine Model (A115-A)  
Typical V  
>2.3 V at V  
(Output V  
Undershoot)  
OHV  
CC  
OH  
= 3.3 V, T = 25°C  
A
Support Mixed-Mode Voltage Operation on  
All Ports  
− 1000-V Charged-Device Model (C101)  
SN54LV02A . . . J OR W PACKAGE  
SN74LV02A . . . D, DB, DGV, NS,  
OR PW PACKAGE  
SN74LV02A . . . RGY PACKAGE  
(TOP VIEW)  
SN54LV02A . . . FK PACKAGE  
(TOP VIEW)  
(TOP VIEW)  
3
2
1
20 19  
18  
1
14  
1Y  
1A  
V
CC  
1
2
3
4
5
6
7
14  
13  
12  
11  
4B  
NC  
4A  
1B  
NC  
2Y  
4
5
6
7
8
1A  
1B  
2Y  
2A  
2B  
13 4Y  
12 4B  
2
3
4
5
6
4Y  
4B  
4A  
17  
16  
1B  
11  
10  
9
4A  
3Y  
3B  
2Y  
15 NC  
NC  
2A  
2A  
10 3Y  
14  
9 10 11 12 13  
3Y  
9
8
2B  
3B  
3A  
7
8
GND  
NC − No internal connection  
description/ordering information  
The ’LV02A devices are quadruple 2-input positive-NOR gates designed for 2-V to 5.5-V V  
operation.  
CC  
The ’LV02A devices perform the Boolean function Y = A + B or Y = A B in positive logic.  
These devices are fully specified for partial-power-down applications using I . The I circuitry disables the  
off  
off  
outputs, preventing damaging current backflow through the devices when they are powered down.  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
PACKAGE  
T
A
QFN − RGY  
SOIC − D  
Reel of 1000  
Tube of 50  
SN74LV02ARGYR  
SN74LV02AD  
LV02A  
LV02A  
Reel of 2500  
Reel of 2000  
Reel of 2000  
Tube of 90  
SN74LV02ADR  
SN74LV02ANSR  
SN74LV02ADBR  
SN74LV02APW  
SN74LV02APWR  
SN74LV02APWT  
SN74LV02ADGVR  
SNJ54LV02AJ  
SOP − NS  
74LV02A  
LV02A  
SSOP − DB  
−40°C to 85°C  
Reel of 2000  
Reel of 250  
Reel of 2000  
Tube of 25  
TSSOP − PW  
LV02A  
TVSOP − DGV  
CDIP − J  
LV02A  
SNJ54LV02AJ  
SNJ54LV102AW  
SNJ54LV02AFK  
−55°C to 125°C  
CFP − W  
Tube of 150  
Tube of 55  
SNJ54LV02AW  
SNJ54LV02AFK  
LCCC − FK  
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design  
guidelines are available at www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 2005, Texas Instruments Incorporated  
ꢌ ꢁ ꢄꢐꢀꢀ ꢔ ꢓꢖ ꢐꢎꢗ ꢒꢀ ꢐ ꢁ ꢔꢓꢐꢍ ꢘꢙ ꢚꢛ ꢜꢝꢞ ꢟꢠꢡ ꢢꢘ ꢞꢝ ꢢꢘꢣ ꢚꢢꢛ ꢏꢎ ꢔ ꢍ ꢌ ꢤꢓ ꢒꢔ ꢁ  
ꢦꢠ  
ꢣꢦ  
ꢧꢣ ꢦ ꢣ ꢠ ꢡ ꢘ ꢡ ꢦ ꢛ ꢪ  
ꢞꢡ  
ꢣꢦ  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

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