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SN74LS374N PDF预览

SN74LS374N

更新时间： 2024-11-20 23:06:19
品牌 Logo 应用领域
德州仪器 - TI 总线驱动器总线收发器触发器锁存器逻辑集成电路光电二极管PC
页数 文件大小 规格书
24页 638K
描述
OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS

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SN74LS374N 技术参数

是否无铅：不含铅是否Rohs认证：符合
生命周期：Active零件包装代码：DIP
包装说明：DIP-20针数：20
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01Factory Lead Time：6 weeks
风险等级：0.56Samacsys Confidence：3
Samacsys Status：ReleasedSamacsys PartID：182104
Samacsys Pin Count：20Samacsys Part Category：Integrated Circuit
Samacsys Package Category：Dual-In-Line PackagesSamacsys Footprint Name：PDIP-N20-1
Samacsys Released Date：2019-09-26 16:05:45Is Samacsys：N
控制类型：ENABLE LOW计数方向：UNIDIRECTIONAL
系列：LSJESD-30 代码：R-PDIP-T20
JESD-609代码：e4长度：25.4 mm
负载电容（CL）：45 pF逻辑集成电路类型：BUS DRIVER
最大I（ol）：0.024 A湿度敏感等级：1
位数：8功能数量：1
端口数量：2端子数量：20
最高工作温度：70 °C最低工作温度：
输出特性：3-STATE输出极性：TRUE
封装主体材料：PLASTIC/EPOXY封装代码：DIP
封装等效代码：DIP20,.3封装形状：RECTANGULAR
封装形式：IN-LINE包装方法：TUBE
峰值回流温度（摄氏度）：260电源：5 V
最大电源电流（ICC）：40 mAProp。Delay @ Nom-Sup：28 ns
传播延迟（tpd）：28 ns认证状态：Not Qualified
座面最大高度：5.08 mm子类别：FF/Latches
最大供电电压 (Vsup)：5.25 V最小供电电压 (Vsup)：4.75 V
标称供电电压 (Vsup)：5 V表面贴装：NO
技术：TTL温度等级：COMMERCIAL
端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)端子形式：THROUGH-HOLE
端子节距：2.54 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED触发器类型：POSITIVE EDGE
宽度：7.62 mmBase Number Matches：1

SN74LS374N 数据手册

 浏览型号SN74LS374N的Datasheet PDF文件第2页浏览型号SN74LS374N的Datasheet PDF文件第3页浏览型号SN74LS374N的Datasheet PDF文件第4页浏览型号SN74LS374N的Datasheet PDF文件第5页浏览型号SN74LS374N的Datasheet PDF文件第6页浏览型号SN74LS374N的Datasheet PDF文件第7页 
SN54LS373, SN54LS374, SN54S373, SN54S374,  
SN74LS373, SN74LS374, SN74S373, SN74S374  
OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS  
SDLS165B – OCTOBER 1975 – REVISED AUGUST 2002  
SN54LS373, SN54LS374, SN54S373,  
SN54S374 . . . J OR W PACKAGE  
SN74LS373, SN74S374 . . . DW, N, OR NS PACKAGE  
Choice of Eight Latches or Eight D-Type  
Flip-Flops in a Single Package  
3-State Bus-Driving Outputs  
Full Parallel Access for Loading  
Buffered Control Inputs  
SN74LS374 . . . DB, DW, N, OR NS PACKAGE  
SN74S373 . . . DW OR N PACKAGE  
(TOP VIEW)  
1
2
3
4
5
6
7
8
9
10  
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
OC  
1Q  
V
CC  
Clock-Enable Input Has Hysteresis to  
Improve Noise Rejection (’S373 and ’S374)  
8Q  
8D  
7D  
7Q  
6Q  
6D  
5D  
5Q  
1D  
P-N-P Inputs Reduce DC Loading on Data  
Lines (’S373 and ’S374)  
2D  
2Q  
3Q  
description  
3D  
These 8-bit registers feature 3-state outputs  
designed specifically for driving highly capacitive  
or relatively low-impedance loads. The  
4D  
4Q  
†
GND  
C
high-impedance  
3-state  
and  
increased  
†
Cfor’LS373and’S373;CLKfor’LS374and’S374.  
high-logic-level drive provide these registers with  
the capability of being connected directly to and  
driving the bus lines in a bus-organized system  
without need for interface or pullup components.  
These devices are particularly attractive for  
implementing buffer registers, I/O ports,  
bidirectional bus drivers, and working registers.  
SN54LS373, SN54LS374, SN54S373,  
SN54S374 . . . FK PACKAGE  
(TOP VIEW)  
3
2
1
20 19  
18  
The eight latches of the ’LS373 and ’S373 are  
transparent D-type latches, meaning that while  
the enable (C or CLK) input is high, the Q outputs  
follow the data (D) inputs. When C or CLK is taken  
low, the output is latched at the level of the data  
that was set up.  
8D  
7D  
7Q  
6Q  
6D  
2D  
2Q  
3Q  
3D  
4D  
4
5
6
7
8
17  
16  
15  
14  
9 10 11 12 13  
The eight flip-flops of the ’LS374 and ’S374 are  
edge-triggered D-type flip-flops. On the positive  
transition of the clock, the Q outputs are set to the  
logic states that were set up at the D inputs.  
†
Cfor’LS373and’S373;CLKfor’LS374and’S374.  
Schmitt-trigger buffered inputs at the enable/clock lines of the ’S373 and ’S374 devices simplify system design  
as ac and dc noise rejection is improved by typically 400 mV due to the input hysteresis. A buffered  
output-control (OC) input can be used to place the eight outputs in either a normal logic state (high or low logic  
levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines  
significantly.  
OC does not affect the internal operation of the latches or flip-flops. That is, the old data can be retained or new  
data can be entered, even while the outputs are off.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 2002, Texas Instruments Incorporated  
On products compliant to MIL-PRF-38535, all parameters are tested  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
unless otherwise noted. On all other products, production  
testing of all parameters.  
processing does not necessarily include testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...24

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SN74LS374N 替代型号

型号 品牌 替代类型 描述 数据表
SN74LS374NE4 TI

完全替代

 OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS
SN74ALS374ANE4 TI

类似代替

 OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS WITH 3-STATE OUTPUTS
SN74ALS374AN TI

类似代替

 OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS WITH 3-STATE OUTPUTS

与SN74LS374N相关器件

型号 品牌 获取价格 描述 数据表
SN74LS374N-00 TI

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 		暂无描述
SN74LS374N1 ROCHESTER

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 		Bus Driver,
SN74LS374N-10 TI

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 		IC LS SERIES, 8-BIT DRIVER, TRUE OUTPUT, PDIP20, Bus Driver/Transceiver
SN74LS374N3 TI

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 		OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS
SN74LS374ND MOTOROLA

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 		LS SERIES, 8-BIT DRIVER, TRUE OUTPUT, PDIP20, 738-03
SN74LS374NDS MOTOROLA

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 		LS SERIES, 8-BIT DRIVER, TRUE OUTPUT, PDIP20, PLASTIC, DIP-20
SN74LS374NE4 TI

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 		OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS
SN74LS374NP3 ROCHESTER

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 		Bus Driver,
SN74LS374NS MOTOROLA

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 		LS SERIES, 8-BIT DRIVER, TRUE OUTPUT, PDIP20, PLASTIC, DIP-20
SN74LS374NSR TI

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 		OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS

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