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SN74LS374 PDF预览

SN74LS374

更新时间: 2024-02-11 22:49:13
品牌 Logo 应用领域
安森美 - ONSEMI 触发器锁存器
页数 文件大小 规格书
8页 99K
描述
Octal Transparent Latch with 3-State Outputs Octal D-Type Flip-Flop with 3-State Output

SN74LS374 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
包装说明:DIP, DIP20,.3Reach Compliance Code:unknown
HTS代码:8542.39.00.01风险等级:5.27
JESD-30 代码:R-PDIP-T20JESD-609代码:e0
逻辑集成电路类型:D FLIP-FLOP功能数量:8
端子数量:20最高工作温度:70 °C
最低工作温度:输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:DIP
封装等效代码:DIP20,.3封装形状:RECTANGULAR
封装形式:IN-LINE电源:5 V
子类别:FF/Latches标称供电电压 (Vsup):5 V
表面贴装:NO技术:TTL
温度等级:COMMERCIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUAL触发器类型:POSITIVE EDGE
Base Number Matches:1

SN74LS374 数据手册

 浏览型号SN74LS374的Datasheet PDF文件第2页浏览型号SN74LS374的Datasheet PDF文件第3页浏览型号SN74LS374的Datasheet PDF文件第4页浏览型号SN74LS374的Datasheet PDF文件第5页浏览型号SN74LS374的Datasheet PDF文件第6页浏览型号SN74LS374的Datasheet PDF文件第7页 
SN74LS373, SN74LS374  
Octal Transparent Latch  
with 3-State Outputs;  
Octal D-Type Flip-Flop  
with 3-State Output  
http://onsemi.com  
The SN74LS373 consists of eight latches with 3-state outputs for  
bus organized system applications. The flip-flops appear transparent  
to the data (data changes asynchronously) when Latch Enable (LE) is  
HIGH. When LE is LOW, the data that meets the setup times is  
latched. Data appears on the bus when the Output Enable (OE) is  
LOW. When OE is HIGH the bus output is in the high impedance state.  
The SN74LS374 is a high-speed, low-power Octal D-type Flip-Flop  
featuring separate D-type inputs for each flip-flop and 3-state outputs  
for bus oriented applications. A buffered Clock (CP) and Output  
Enable (OE) is common to all flip-flops. The SN74LS374 is  
manufactured using advanced Low Power Schottky technology and is  
compatible with all ON Semiconductor TTL families.  
LOW  
POWER  
SCHOTTKY  
MARKING  
DIAGRAMS  
SN74LS37xN  
AWLYYWW  
Eight Latches in a Single Package  
3-State Outputs for Bus Interfacing  
Hysteresis on Latch Enable  
Edge-Triggered D-Type Inputs  
1
20  
1
PDIP–20  
N SUFFIX  
CASE 738  
Buffered Positive Edge-Triggered Clock  
Hysteresis on Clock Input to Improve Noise Margin  
Input Clamp Diodes Limit High Speed Termination Effects  
LS37x  
AWLYYWW  
20  
GUARANTEED OPERATING RANGES  
1
1
Symbol  
Parameter  
Supply Voltage  
Min  
4.75  
0
Typ  
5.0  
25  
Max  
5.25  
70  
Unit  
V
SOIC–20  
DW SUFFIX  
CASE 751D  
V
CC  
T
A
Operating Ambient  
Temperature Range  
°C  
I
Output Current – High  
Output Current – Low  
–2.6  
24  
mA  
mA  
OH  
I
OL  
74LS37x  
AWLYWW  
20  
1
SOEIAJ–20  
1
M SUFFIX  
CASE 967  
x
= 3 or 4  
A
= Assembly Location  
WL = Wafer Lot  
YY = Year  
WW = Work Week  
ORDERING INFORMATION  
See detailed ordering and shipping information in the package  
dimensions section on page 6 of this data sheet.  
Semiconductor Components Industries, LLC, 2001  
1
Publication Order Number:  
October, 2001 – Rev. 8  
SN74LS373/D  

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