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SN74LS240DBR PDF预览

SN74LS240DBR

更新时间: 2024-11-08 23:06:19
品牌 Logo 应用领域
德州仪器 - TI 总线驱动器总线收发器逻辑集成电路光电二极管输出元件
页数 文件大小 规格书
16页 247K
描述
OCTAL BUFFERS AND LINE DRIVERS WITH 3-STATE OUTPUTS

SN74LS240DBR 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:SSOP
包装说明:SSOP, SSOP20,.3针数:20
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01Factory Lead Time:6 weeks
风险等级:1.37Is Samacsys:N
控制类型:ENABLE LOW计数方向:UNIDIRECTIONAL
系列:LSJESD-30 代码:R-PDSO-G20
JESD-609代码:e4长度:7.2 mm
负载电容(CL):45 pF逻辑集成电路类型:BUS DRIVER
最大I(ol):0.024 A湿度敏感等级:1
位数:4功能数量:2
端口数量:2端子数量:20
最高工作温度:70 °C最低工作温度:
输出特性:3-STATE输出极性:INVERTED
封装主体材料:PLASTIC/EPOXY封装代码:SSOP
封装等效代码:SSOP20,.3封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, SHRINK PITCH包装方法:TR
峰值回流温度(摄氏度):260电源:5 V
最大电源电流(ICC):50 mAProp。Delay @ Nom-Sup:18 ns
传播延迟(tpd):18 ns认证状态:Not Qualified
座面最大高度:2 mm子类别:Bus Driver/Transceivers
最大供电电压 (Vsup):5.25 V最小供电电压 (Vsup):4.75 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:TTL温度等级:COMMERCIAL
端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)端子形式:GULL WING
端子节距:0.65 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:5.3 mm
Base Number Matches:1

SN74LS240DBR 数据手册

 浏览型号SN74LS240DBR的Datasheet PDF文件第2页浏览型号SN74LS240DBR的Datasheet PDF文件第3页浏览型号SN74LS240DBR的Datasheet PDF文件第4页浏览型号SN74LS240DBR的Datasheet PDF文件第5页浏览型号SN74LS240DBR的Datasheet PDF文件第6页浏览型号SN74LS240DBR的Datasheet PDF文件第7页 
SN54LS240, SN54LS241, SN54LS244, SN54S240, SN54S241, SN54S244  
SN74LS240, SN74LS241, SN74LS244, SN74S240, SN74S241, SN74S244  
OCTAL BUFFERS AND LINE DRIVERS WITH 3-STATE OUTPUTS  
SDLS144B – APRIL 1985 – REVISED FEBRUARY 2002  
SN54LS’, SN54S’ . . . J OR W PACKAGE  
3-State Outputs Drive Bus Lines or Buffer  
Memory Address Registers  
SN74LS240, SN74LS244 . . . DB, DW, N, OR NS PACKAGE  
SN74LS241 . . . DW, N, OR NS PACKAGE  
SN74S’ . . . DW OR N PACKAGE  
PNP Inputs Reduce DC Loading  
(TOP VIEW)  
Hysteresis at Inputs Improves Noise  
Margins  
1G  
1A1  
2Y4  
1A2  
2Y3  
1A3  
2Y2  
1A4  
2Y1  
GND  
V
CC  
2G/2G  
1
2
3
4
5
6
7
8
9
10  
20  
19  
18  
17  
16  
15  
14  
description  
1Y1  
2A4  
1Y2  
2A3  
These octal buffers and line drivers are designed  
specifically to improve both the performance and  
density of three-state memory address drivers,  
clock drivers, and bus-oriented receivers and  
transmitters. The designer has a choice of  
selected combinations of inverting and  
noninverting outputs, symmetrical, active-low  
output-control (G) inputs, and complementary  
output-control (G and G) inputs. These devices  
featurehighfan-out, improvedfan-in, and400-mV  
noise margin. The SN74LS’ and SN74S’ devices  
can be used to drive terminated lines down to  
133 .  
1Y3  
13 2A2  
12 1Y4  
11  
2A1  
2G for ’LS241 and ’S241 or 2G for all other drivers.  
SN54LS’, SN54S’ . . . FK PACKAGE  
(TOP VIEW)  
3
2
1
20 19  
18  
1Y1  
2A4  
1Y2  
2A3  
1Y3  
1A2  
2Y3  
1A3  
2Y2  
1A4  
4
5
6
7
8
17  
16  
15  
14  
9 10 11 12 13  
2G for ’LS241 and ’S241 or 2G for all other drivers.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 2002, Texas Instruments Incorporated  
On products compliant to MIL-PRF-38535, all parameters are tested  
unless otherwise noted. On all other products, production  
processing does not necessarily include testing of all parameters.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

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