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SN74LS194AJS PDF预览

SN74LS194AJS

更新时间: 2024-11-26 13:13:51
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA 移位寄存器
页数 文件大小 规格书
6页 217K
描述
LS SERIES, 4-BIT BIDIRECTIONAL PARALLEL IN PARALLEL OUT SHIFT REGISTER, TRUE OUTPUT, CDIP16, CERAMIC, DIP-16

SN74LS194AJS 技术参数

是否Rohs认证:不符合生命周期:Obsolete
零件包装代码:DIP包装说明:DIP, DIP16,.3
针数:16Reach Compliance Code:unknown
HTS代码:8542.39.00.01风险等级:5.1
Is Samacsys:N其他特性:HOLD MODE
计数方向:BIDIRECTIONAL系列:LS
JESD-30 代码:R-GDIP-T16JESD-609代码:e0
长度:19.495 mm逻辑集成电路类型:PARALLEL IN PARALLEL OUT
位数:4功能数量:1
端子数量:16最高工作温度:70 °C
最低工作温度:输出极性:TRUE
封装主体材料:CERAMIC, GLASS-SEALED封装代码:DIP
封装等效代码:DIP16,.3封装形状:RECTANGULAR
封装形式:IN-LINE峰值回流温度(摄氏度):NOT SPECIFIED
电源:5 V传播延迟(tpd):26 ns
认证状态:Not Qualified座面最大高度:5.08 mm
子类别:Shift Registers最大供电电压 (Vsup):5.25 V
最小供电电压 (Vsup):4.75 V标称供电电压 (Vsup):5 V
表面贴装:NO技术:TTL
温度等级:COMMERCIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
触发器类型:POSITIVE EDGE宽度:7.62 mm
最小 fmax:36 MHzBase Number Matches:1

SN74LS194AJS 数据手册

 浏览型号SN74LS194AJS的Datasheet PDF文件第2页浏览型号SN74LS194AJS的Datasheet PDF文件第3页浏览型号SN74LS194AJS的Datasheet PDF文件第4页浏览型号SN74LS194AJS的Datasheet PDF文件第5页浏览型号SN74LS194AJS的Datasheet PDF文件第6页 
SN54/74LS194A  
4-BIT BIDIRECTIONAL  
UNIVERSAL SHIFT REGISTER  
The SN54/74LS194A is a High Speed 4-Bit Bidirectional Universal Shift  
Register. As a high speed multifunctional sequential building block, it is useful  
in a wide variety of applications. It may be used in serial-serial, shift left, shift  
right, serial-parallel, parallel-serial, and parallel-parallel data register trans-  
fers. The LS194A is similar in operation to the LS195A Universal Shift  
Register, with added features of shift left without external connections and  
hold (do nothing) modes of operation. It utilizes the Schottky diode clamped  
process to achieve high speeds and is fully compatible with all Motorola TTL  
families.  
4-BIT BIDIRECTIONAL  
UNIVERSAL SHIFT REGISTER  
LOW POWER SCHOTTKY  
Typical Shift Frequency of 36 MHz  
Asynchronous Master Reset  
J SUFFIX  
CERAMIC  
CASE 620-09  
Hold (Do Nothing) Mode  
Fully Synchronous Serial or Parallel Data Transfers  
Input Clamp Diodes Limit High Speed Termination Effects  
16  
1
N SUFFIX  
PLASTIC  
CONNECTION DIAGRAM DIP (TOP VIEW)  
CASE 648-08  
16  
1
D SUFFIX  
SOIC  
CASE 751B-03  
16  
1
ORDERING INFORMATION  
SN54LSXXXJ  
Ceramic  
SN74LSXXXN Plastic  
SN74LSXXXD SOIC  
PIN NAMES  
LOADING (Note a)  
HIGH  
LOW  
S , S  
Mode Control Inputs  
Parallel Data Inputs  
0.5 U.L.  
0.5 U.L.  
0.5 U.L.  
0.5 U.L.  
0.5 U.L.  
0.5 U.L.  
10 U.L.  
0.25 U.L.  
0.25 U.L.  
0.25 U.L.  
0.25 U.L.  
0.25 U.L.  
0.25 U.L.  
5 (2.5) U.L.  
0
1
3
P P  
0
D
D
Serial (Shift Right) Data Input  
Serial (Shift Left) Data Input  
Clock (Active HIGH Going Edge) Input  
Master Reset (Active LOW) Input  
Parallel Outputs (Note b)  
SR  
SL  
CP  
MR  
Q Q  
0
3
NOTES:  
a. 1 TTL Unit Load (U.L.) = 40 µA HIGH/1.6 mA LOW.  
b. The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial (74)  
b. Temperature Ranges.  
FAST AND LS TTL DATA  
5-360  

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