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SN74LS174N PDF预览

SN74LS174N

更新时间: 2024-11-08 23:06:19
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA 触发器锁存器逻辑集成电路光电二极管
页数 文件大小 规格书
3页 80K
描述
HEX D FLIP-FLOP

SN74LS174N 技术参数

生命周期:Transferred零件包装代码:DIP
包装说明:DIP, DIP16,.3针数:16
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.07Is Samacsys:N
系列:LSJESD-30 代码:R-PDIP-T16
JESD-609代码:e0长度:19.175 mm
负载电容(CL):15 pF逻辑集成电路类型:D FLIP-FLOP
最大频率@ Nom-Sup:30000000 Hz最大I(ol):0.008 A
位数:6功能数量:1
端子数量:16最高工作温度:70 °C
最低工作温度:输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:DIP
封装等效代码:DIP16,.3封装形状:RECTANGULAR
封装形式:IN-LINE电源:5 V
最大电源电流(ICC):26 mA传播延迟(tpd):30 ns
认证状态:Not Qualified座面最大高度:4.44 mm
子类别:FF/Latches最大供电电压 (Vsup):5.25 V
最小供电电压 (Vsup):4.75 V标称供电电压 (Vsup):5 V
表面贴装:NO技术:TTL
温度等级:COMMERCIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUAL触发器类型:POSITIVE EDGE
宽度:7.62 mm最小 fmax:30 MHz
Base Number Matches:1

SN74LS174N 数据手册

 浏览型号SN74LS174N的Datasheet PDF文件第2页浏览型号SN74LS174N的Datasheet PDF文件第3页 
SN54/74LS174  
HEX D FLIP-FLOP  
The LSTTL/MSI SN54/74LS174 is a high speed Hex D Flip-Flop. The  
device is used primarily as a 6-bit edge-triggered storage register. The  
information on the D inputs is transferred to storage during the LOW to HIGH  
clock transition. The device has a Master Reset to simultaneously clear all  
flip-flops. The LS174 is fabricated with the Schottky barrier diode process for  
high speed and is completely compatible with all Motorola TTL families.  
HEX D FLIP-FLOP  
LOW POWER SCHOTTKY  
Edge-Triggered D-Type Inputs  
Buffered-Positive Edge-Triggered Clock  
Asynchronous Common Reset  
Input Clamp Diodes Limit High Speed Termination Effects  
J SUFFIX  
CERAMIC  
CONNECTION DIAGRAM DIP (TOP VIEW)  
CASE 620-09  
V
Q
D
D
Q
D
Q
3
CP  
9
CC  
5
5
4
4
3
16  
16  
15  
14  
13  
12  
11  
10  
1
NOTE:  
The Flatpak version  
has the same pinouts  
(Connection Diagram) as  
the Dual In-Line Package.  
N SUFFIX  
PLASTIC  
CASE 648-08  
16  
1
2
3
4
5
6
8
7
1
MR  
Q
D
D
Q
D
Q
2
GND  
0
0
1
1
2
D SUFFIX  
SOIC  
CASE 751B-03  
PIN NAMES  
LOADING (Note a)  
16  
HIGH  
LOW  
1
D D  
0
Data Inputs  
0.5 U.L.  
0.5 U.L.  
0.5 U.L.  
10 U.L.  
0.25 U.L.  
0.25 U.L.  
0.25 U.L.  
5
CP  
Clock (Active HIGH Going Edge) Input  
Master Reset (Active LOW) Input  
Outputs (Note b)  
ORDERING INFORMATION  
MR  
Q Q  
0
5 (2.5) U.L.  
5
SN54LSXXXJ  
Ceramic  
SN74LSXXXN Plastic  
SN74LSXXXD SOIC  
NOTES:  
a. 1 TTL Unit Load (U.L.) = 40 µA HIGH/1.6 mA LOW.  
b. The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial (74)  
b. Temperature Ranges.  
LOGIC SYMBOL  
LOGIC DIAGRAM  
3
4
6
11 13 14  
MR CP  
D
D
D
D
D
D
0
5
4
3
2
1
1
9
14  
13  
11  
6
4
3
D
D
D
D
D
D
0
1
1
2
2
3
3
4
4
5
5
9
1
CP  
MR  
Q
Q
Q
Q
Q
Q
0
D
Q
D
D
Q
D
D
Q
D
D
Q
D
D
Q
D
D
Q
D
CP  
CP  
CP  
CP  
CP  
CP  
C
C
C
C
C
C
2
5
7 10 12 15  
15  
5
12  
10  
7
5
Q
1
2
V
= PIN 16  
Q
Q
Q
Q
Q
CC  
GND = PIN 8  
4
0
3
2
V
= PIN 16  
CC  
GND = PIN 8  
= PIN NUMBERS  
FAST AND LS TTL DATA  
5-1  

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