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SN74LS161ADR2 PDF预览

SN74LS161ADR2

更新时间: 2024-02-22 13:54:51
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA 光电二极管输出元件逻辑集成电路触发器
页数 文件大小 规格书
6页 79K
描述
LS SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT UP BINARY COUNTER, PDSO16, SOIC-16

SN74LS161ADR2 技术参数

是否Rohs认证: 不符合生命周期:Transferred
包装说明:SOP, SOP16,.25Reach Compliance Code:unknown
HTS代码:8542.39.00.01风险等级:5.67
其他特性:TCO OUTPUT计数方向:UP
系列:LSJESD-30 代码:R-PDSO-G16
JESD-609代码:e0长度:9.9 mm
负载电容(CL):15 pF负载/预设输入:YES
逻辑集成电路类型:BINARY COUNTER最大频率@ Nom-Sup:25000000 Hz
最大I(ol):0.008 A工作模式:SYNCHRONOUS
位数:4功能数量:1
端子数量:16最高工作温度:70 °C
最低工作温度:封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP16,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
包装方法:TAPE AND REEL电源:5 V
最大电源电流(ICC):32 mA传播延迟(tpd):27 ns
认证状态:Not Qualified座面最大高度:1.75 mm
子类别:Counters最大供电电压 (Vsup):5.25 V
最小供电电压 (Vsup):4.75 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:TTL
温度等级:COMMERCIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL触发器类型:POSITIVE EDGE
宽度:3.9 mm最小 fmax:25 MHz
Base Number Matches:1

SN74LS161ADR2 数据手册

 浏览型号SN74LS161ADR2的Datasheet PDF文件第2页浏览型号SN74LS161ADR2的Datasheet PDF文件第3页浏览型号SN74LS161ADR2的Datasheet PDF文件第4页浏览型号SN74LS161ADR2的Datasheet PDF文件第5页浏览型号SN74LS161ADR2的Datasheet PDF文件第6页 
SN54/74LS160A  
SN54/74LS161A  
SN54/74LS162A  
SN54/74LS163A  
BCD DECADE COUNTERS/  
4-BIT BINARY COUNTERS  
The LS160A/161A/162A/163A are high-speed 4-bit synchronous count-  
ers. They are edge-triggered, synchronously presettable, and cascadable  
MSI building blocks for counting, memory addressing, frequency division and  
other applications. The LS160A and LS162A count modulo 10 (BCD). The  
LS161A and LS163A count modulo 16 (binary.)  
BCD DECADE COUNTERS/  
4-BIT BINARY COUNTERS  
The LS160A and LS161A have an asynchronous Master Reset (Clear)  
input that overrides, and is independent of, the clock and all other control  
inputs. TheLS162AandLS163AhaveaSynchronousReset(Clear)inputthat  
overrides all other control inputs, but is active only during the rising clock  
edge.  
LOW POWER SCHOTTKY  
BCD (Modulo 10)  
LS160A  
Binary (Modulo 16)  
LS161A  
J SUFFIX  
CERAMIC  
CASE 620-09  
Asynchronous Reset  
Synchronous Reset  
LS162A  
LS163A  
16  
1
Synchronous Counting and Loading  
Two Count Enable Inputs for High Speed Synchronous Expansion  
Terminal Count Fully Decoded  
Edge-Triggered Operation  
Typical Count Rate of 35 MHz  
ESD > 3500 Volts  
N SUFFIX  
PLASTIC  
CASE 648-08  
16  
1
CONNECTION DIAGRAM DIP (TOP VIEW)  
V
TC  
15  
Q
Q
Q
Q
3
CET  
10  
PE  
9
CC  
0
1
2
D SUFFIX  
16  
14  
13  
12  
11  
SOIC  
CASE 751B-03  
NOTE:  
16  
The Flatpak version  
has the same pinouts  
(Connection Diagram) as  
the Dual In-Line Package.  
1
ORDERING INFORMATION  
*MR for LS160A and LS161A  
*SR for LS162A and LS163A  
SN54LSXXXJ Ceramic  
SN74LSXXXN Plastic  
SN74LSXXXD SOIC  
1
2
3
4
5
6
8
7
*R  
CP  
P
P
P
P
3
CEP GND  
0
1
2
PIN NAMES  
LOADING (Note a)  
LOGIC SYMBOL  
HIGH  
LOW  
9
3
4
5
6
PE  
Parallel Enable (Active LOW) Input  
Parallel Inputs  
Count Enable Parallel Input  
Count Enable Trickle Input  
Clock (Active HIGH Going Edge) Input  
Master Reset (Active LOW) Input  
Synchronous Reset (Active LOW) Input  
Parallel Outputs (Note b)  
1.0 U.L.  
0.5 U.L.  
0.5 U.L.  
1.0 U.L.  
0.5 U.L.  
0.5 U.L.  
1.0 U.L.  
10 U.L.  
10 U.L.  
0.5 U.L.  
0.25 U.L.  
0.25 U.L.  
0.5 U.L.  
0.25 U.L.  
0.25 U.L.  
0.5 U.L.  
P P  
0
3
PE  
CEP  
P
P
P
P
CEP  
CET  
CP  
0
1
2
3
7
TC  
15  
CET  
CP  
10  
2
MR  
SR  
*R  
Q
Q
Q
Q
2 3  
0
1
Q Q  
5 (2.5) U.L.  
5 (2.5) U.L.  
0
3
TC  
Terminal Count Output (Note b)  
1
14 13 12 11  
= PIN 16  
NOTES:  
a) 1 TTL Unit Load (U.L.) = 40 µA HIGH/1.6 mA LOW.  
b) The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial (74)  
Temperature Ranges.  
V
CC  
GND = PIN 8  
*MR for LS160A and LS161A  
*SR for LS162A and LS163A  
FAST AND LS TTL DATA  
5-1  

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